Microchip Technology Inc.

Paul Fest

James Walls

Jacob Lee Williams

Josh Kaufman

Greg Dix

A process is provided for forming an integrated thin film resistor (TFR) in an integrated circuit (IC) device including IC elements and IC element contacts. A TFR film layer and TFR dielectric layer are formed over the IC structure, and a wet etch is performed to define a dielectric cap with sloped lateral edges over the TFR film layer. Exposed portions of the TFR film layer are etched to define a TFR element. A TFR contact etch forms contact openings over the TFR element, and a metal layer is formed to form metal layer connections to the IC element contacts and the TFR element. The sloped edges of the dielectric cap may improve the removal of metal adjacent the TFR element to prevent electrical shorts in the completed device. A TFR anneal to reduce a TCR of the TFR is performed at any suitable time before forming the metal layer.

Thin film resistor (TFR) formed in an integrated circuit device using wet etching of a dielectric cap

A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. At least one TFR cap layer is formed, and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer(s), e.g., SiN cap and/or oxide cap formed over the TFR film, may (a) provide an etch stop during the TFR contact etch and/or (b) provide a hardmask during the TFR etch, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer.

Thin film resistor (TFR) formed in an integrated circuit device using TFR cap layer(s) as an etch stop and/or hardmask

A process is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. An oxide cap is formed over the TFR film, which acts as a hardmask during a TFR etch of the TFR film to define a TFR element, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer. TFR edge spacers may be formed over lateral edges of the TFR element to insulate such TFR element edges. TFR contact openings are etched in the oxide cap over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element.

Thin film resistor (TFR) formed in an integrated circuit device using an oxide cap layer as a TFR etch hardmask

A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.

Forming a thin film resistor (TFR) in an integrated circuit device

A method is provided for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device. A first dielectric layer is deposited on an integrated circuit (IC) structure including conductive contacts, a resistive film (e.g., comprising SiCCr, SiCr, CrSiN, TaN, TaSi, or TiN) is deposited over the first dielectric layer, the resistive film is etched to define the dimensions of the resistive film, and a second dielectric layer is deposited over the resistive film, such that the resistive film is sandwiched between the first and second dielectric layers. An interconnect trench layer may be deposited over the second dielectric layer and etched, e.g., using a single mask, to define openings that expose surfaces of the IC structure contacts and the resistive film. The openings may be filled with a conductive interconnect material, e.g., copper, to contact the exposed surfaces of the conductive contacts and the resistive film.

Systems and methods for forming a thin film resistor integrated in an integrated circuit device

A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors.

Spacer enabled poly gate

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Resistive memory cell with sloped bottom electrode

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.

Resistive memory cell having a reduced conductive path area

A method of forming a resistive memory cell, e.g., CBRAM or ReRAM, includes forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region. An electrically insulating mini-spacer region is formed adjacent the bottom electrode, and an electrolyte region and top electrode are formed over the bottom electrode and mini-spacer element(s) to define a memory element. The memory element defines a conductive filament/vacancy chain path from the bottom electrode pointed tip region to the top electrode via the electrolyte region. The mini-spacer elements decreases the effective area, or 'confinement zone,' for the conductive filament/vacancy chain path, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces.

Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

Resistive memory cell having a single bottom electrode and two top electrodes

A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create 'fence conductors.' Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.

Forming fence conductors using spacer etched trenches

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Resistive memory cell with bottom electrode having a sloped side wall

A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell.

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Chandler, AZ, United States of America

Paul Fest