Stmicroelectronics Gmbh

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Paul Ferreira

John H Zhang

Ronald Kevin Sampson

Walter Kleemeier

Philippe Coronel

Francois Leverd

Phillipe Coronel

A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Device and method for alignment of vertically stacked wafers and die

A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.

Method for protecting the gate of a transistor and corresponding integrated circuit

Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

CMP techniques for overlapping layer removal

A method for forming contact openings in various locations of the upper surface of an integrated circuit having raised areas, critical openings having to be formed between two neighboring raised areas, including the steps of covering the entire structure with a first protection layer; forming non-critical openings in the first protection layer; coating the structure with a second protection layer; performing an oblique irradiation so that the second protection layer is not irradiated at the bottom of the regions located between two raised areas; removing the non-irradiated portions of the second protection layer; removing the portions of the first protection layer located under the second protection layer at the locations where this second protection layer has been removed; and removing the irradiated portions of the second protection layer.

Method for forming contact openings on a MOS integrated circuit

The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of regions of the surface portion, the two groups of regions being mutually complementary with respect to the surface portion, the process making it possible to use only a single operation of positioning a mask which differentiates the regions of the first and second groups of regions, using the same protective materials for the regions of each group of regions against the effects of the treatment intended for the regions of the other group of regions. Application to the fabrication of semiconductor products.

Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process

The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

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Barraux, France

Paul Ferreira