Standard Microsystems Corporation

Pacesetter, Inc.

Cactus Semiconductor, Inc.

Paul F Illegems

Srinivas Kumar Pulijala

Eric Christophe Labbe

Cliff C Nixon

Described herein are implantable medical devices (IMDs), and methods for use therewith, that enable monitoring of impedance associated with a pathway (e.g., including a lead) used to selectively deliver stimulation pulses to patient tissue. A method involves measuring or storing a first voltage indicative of the energy stored on a reservoir capacitor (Cres) just prior to a stimulation pulse being delivered via the pathway, as well as measuring or storing a second voltage indicative of the energy stored on the Cres just after the stimulation pulse is delivered via the pathway. The method also includes monitoring the impedance associated with the pathway based on a difference between the first and second voltages, which may involve determining a count value indicative of how long it takes to discharge the first voltage to drop to the second voltage, wherein the count value is a surrogate of the impedance associated with the pathway.

Lead impedance monitoring for an implantable medical device

A system, method, and circuit to monitor a compliance voltage in an implantable stimulator device. An implantable medical device with a compliance voltage detector to monitor the voltage used by an output current source/sink circuit to ensure proper circuit performance while limiting power use.

Compliance voltage detector circuit

A driver circuit, that provides slew rate control of its output voltage, including a current generator, an output transistor, and optionally, a capacitor. The current generator has an input port, an output port and reference port. The output port couples to the gate of the output transistor. The capacitor couples between the gate and drain of the output transistor. The current generator controls a current Iflowing through the output port based on an input voltage at the input port. The current generator limits the absolute value of the current Ito be less than or equal to a maximum determined by a reference current Iref provided at the reference port. Modifications may be made to the driver circuit to limit the output current (e.g., as a function of the output voltage) and to make the slew rate limit independent of the gate-drain capacitance of the output transistor.

Driver with accurately controlled slew rate and limited current

A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage.

Oscillator stabilized for temperature and power supply variations

A power-on-reset (POR) circuit may comprise a first circuit powered by a first supply voltage and configured to generate a second supply voltage based on the first supply voltage, the second supply voltage having a nominal value lower than a nominal value of the first supply voltage. The POR circuit may also include a second circuit powered by the second supply voltage and configured to generate a POR signal. The second circuit may be configured to assert the POR signal when the second supply voltage reaches a value that is sufficiently high for the second circuit to become operational, keep the POR signal asserted until the first supply voltage reaches a second value that is higher than the nominal value of the second supply voltage by a specified difference voltage value, and deassert the POR signal once the first supply voltage reaches the second value.

Power-up control for very low-power systems

An improved current source may provide an improvement over a typical &#x394;V-type current source. The improved current source may comprise two branches. A first branch may be configured to generate a PTC (proportional to absolute temperature) current based on a &#x394;Vdeveloped across a resistor. A second branch may be configured to generate an NTC (inversely proportional to absolute temperature) current. The PTC current and NTC current may be combined to obtain a third current having a magnitude that is the sum of the respective magnitudes of the PTC current and the NTC current, and a temperature coefficient that is a combination of the respective temperature coefficients of the PTC current and NTC current. The current source may be configured to generate the NTC current and PTC current to be substantially insensitive to variations in the supply voltage.

Temperature and supply independent CMOS current source

An electronic circuit may comprise an input stage powered by a supply voltage and configured to receive a reference signal. The circuit may further comprise an output stage powered by the supply voltage and coupled to the input stage, and configured to generate an error signal based on: the reference signal, and a feedback signal based on an output signal. The circuit may also include a pass transistor powered by the supply voltage and configured to generate the output signal based on the error signal. A capacitor coupled between the supply voltage and the output stage may increase the current flowing in the output stage, resulting in the output stage conducting current even during a rising edge of the supply voltage, preventing the output signal from reaching the level of the supply voltage during the rising edge of the supply voltage.

Method for improving power-supply rejection

An electronic circuit. The electronic circuit includes a pass transistor having a channel coupled between an input node and an output node. An error circuit is coupled thereto and configured to control the amount of current flowing through the pass transistor. The electronic circuit may further include a feedback node. A current limiting circuit is coupled to both the feedback node and the error circuit. The current limiting circuit is configured to limit an amount of current provided to the pass transistor by the error circuit based on a on a feedback voltage present on the feedback node and a current through a current mirror circuit, and therefore limits the output current provided by the electronic circuit.

Current limiting circuit

A regulator circuit may be configured to operate with multiple power supplies. The regulator circuit may be configured to receive an input voltage and provide a regulated output voltage at an output terminal as a function of the input voltage. The regulator may include at least two drivers. A first driver may have a driver output coupled to the output terminal and have a supply terminal coupled to a high power supply, and a second driver may have a driver output coupled to the output terminal and have a supply terminal coupled to a low power supply. A selector circuit may be configured to compare the input voltage with a control voltage that has a magnitude just below a magnitude of the low power supply, to determine which driver to select from the first driver and the second driver, and enable either the first driver output or the second driver output to be active according to which driver has been selected. The regulator circuit may be configured to operate with any number of power supplies by including corresponding drivers and selection logic in the selector circuit.

Regulator circuit with multiple supply voltages

A level-shifter circuit configured to transfer data between two voltage supply domains may eliminate crowbar current while simultaneously providing a valid output signal. The level-shifter circuit may transfer a data signal between the two voltage domains using a latch that is capable of maintaining its output level&#x2014;based on the destination supply rail&#x2014;to correspond to the same state to which the level of the input signal&#x2014;based on the originating supply rail&#x2014;corresponds, even when the originating supply is decreased to a zero-volt state, or to a voltage equivalent to a low state. During normal operation, when both power supplies are available, the signal at the output of the latch, and hence at the output of the level-shifter circuit may toggle to always track the input signal. Thus, the level of the signal at the output of the level-shifter may always represent the same state (e.g. binary value) as the level of the input signal, during normal operation and also when the originating power supply is powered down.

Level shifter with memory interfacing two supply domains

A three-level detector circuit may comprise an input node and a pair of diode-connected transistors having respective drain terminals coupled to the input node. The pair of diode-connected transistors may be configured to set a voltage if the input voltage at the input node corresponds to an open input. The three-level detector circuit may further comprise a pair of inverting stages coupled to the input node, the pair of inverting stages configured to distinguish between low, high, and/or open inputs. The three-level detector circuit may also comprise a pair of latches, e.g. D-flip-flops, each of the pair of latches having a respective input coupled to a respective output of a respective one of the pair of inverting stages, and each of the pair of latches configured to latch a present state of the input in detection mode. In one set of embodiments, the three-level detector circuit is operable to cease conducting current after the present state of the input has been latched.

Low power three-level detector

A driver circuit with variable output voltage and current. A source input terminal of the driver circuit may receive a source control signal. A voltage control circuit may drive one of the terminals of a first switch to a source voltage. If the source input terminal receives an asserted source control signal, the first switch is turned on and the voltage control circuit drives an output terminal of the driver circuit to the source voltage. A source current mirror may regulate a source current provided to the output terminal of the driver circuit. A sink input terminal of the driver circuit may receive a sink control signal. If the sink input terminal receives an asserted sink control signal, a second switch is turned on and the output terminal is driven to a sink voltage. A sink current mirror may regulate a sink current provided to output terminal of the driver circuit.

Driver with variable output voltage and current

Various embodiments of a voltage level detector implemented as an integrated circuit whose trip point is approximately constant over variations in temperature as well as variations in transistor fabrication parameters are disclosed along with a differential amplifier whose input offset voltage is highly immune to said variations. In one embodiment, a voltage generator supplies a composite voltage to the gate of the tail current transistor of the voltage level detector or differential amplifier. The first component of the voltage is approximately equal to the threshold voltage of NMOS transistors comprised in the device over variations in operating temperature as well as variations in transistor fabrication parameters while the second component is approximately constant with respect to said variations. When applied to the gate of the tail current transistor, the first component may turn the transistor on in spite of the above-mentioned parametric variations.

Amplifier with accurate built-in threshold

In one embodiment, a system comprises a programming unit coupled to at least one programmable fuse and configured to program the programmable fuse. In addition, the system comprises a monitoring circuit coupled to the programmable fuse and configured to monitor electrical characteristics associated with the programmable fuse while the programmable fuse is being programmed. In one embodiment, the monitoring circuit is configured to detect a voltage associated with the programmable fuse. Furthermore, the monitoring circuit is configured to compare the detected voltage associated with the programmable fuse with a predetermined voltage value (i.e., endpoint detection). If the detected voltage is equal to or less than the predetermined voltage value, the monitoring circuit is configured to change a state of a control signal to stop the programming of the programmable fuse. Otherwise, the programming unit continues to program the programmable fuse.

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Tucson, AZ, United States of America

Paul F Illegems