Analog Devices,inc.

Oregon State University

Paul F Ferguson, Jr

Robert W Adams

Apparajan Ganesan

Michael Mueck

David H Robertson

Wai L Lee

Scott Vincelette

Gangadhar Burra

James M Wilson

Thomas James Barber, Jr

Tom W Kwan

Jeffrey Carl Gealow

Gabor C Temes

Dolly Y Wu

Stacy Ho

Norman D Grant

Xavier Haurie

Yunteng Huang

A wireless terminal circuit includes a variable high frequency clock oscillator that provides a high frequency clock signal and a fixed low frequency clock oscillator that provides a low frequency clock signal. A phase-locked loop adjusts a ratio of the frequency of the high frequency clock signal to the low frequency clock signal by adjusting the frequency of the high frequency clock signal. The phase locked loop includes a divider for dividing the high frequency clock signal, the divide ratio of which divider is controlled by a sigma-delta modulator. A wireless terminal local oscillator calibration circuit includes a frequency control circuit including both the high frequency clock oscillator and the low frequency clock oscillator. The calibration circuit also includes a loop circuit that receives a base station clock signal and provides a control signal to the frequency control circuit to adjust the ratio of the frequency of the high frequency clock signal to the frequency of the low frequency clock signals until the high frequency clock signal is calibrated to the base station clock signal.

Timing and frequency control method and circuit for digital wireless telephone system terminals

A digital to analog converter system is disclosed for receiving an input signal and a sign bit signal that is indicative of the sign of the input signal. The digital to analog converter system includes first and second pairs of resistor strings, and first and second switching networks. A first one of the first pair of resistor strings is adapted for coupling between a first voltage potential and an intermediate node. The first switching network is adapted to couple a voltage produced across a selected one of resistors in the first string across the second one of the resistor strings. The resistors in the second resistor string producing voltages in response to current passing from the first resistor string to the second resistor string through the first switching network. A third one of the second pair of resistor strings is adapted for coupling between a second voltage potential and the intermediate node. The second switching network is adapted to couple a voltage produced across a selected one of resistors in the third string across the fourth one of the resistor strings. The resistors in the fourth resistor string produce voltages in response to current passing from the third resistor string to the fourth resistor string through the second switching network.

Balanced dual resistor string digital to analog converter system and method

A dual-mode delta-sigma analog to digital converter system is disclosed that uses a feed forward modulator and includes a low frequency resonator circuit and a high frequency resonator circuit and includes a feed-forward path from the final integrator in the high-frequency resonator circuit to a summer. The digital converter system includes a selection unit for permitting the high frequency resonator circuit and the low frequency resonator circuit to be employed in a first mode of operation. The system also permits the high frequency resonator circuit and the feed-forward path from the final integrator in the high-frequency resonator circuit to the summer to be disabled in a second mode of operation.

Dual-mode delta-sigma analog to digital converter system and method

A switched capacitor integrator system includes an input cascoded amplifier circuit; a summing junction; an integrating switched capacitor circuit connected to the output of the input cascoded amplifier circuit and to the summing junction; the integrating switched capacitor circuit including an input switched capacitor circuit responsive to an input and connected to the summing junction; and a correlated double sampling capacitor circuit including an offset capacitor interconnected between the summing junction and the input of the input cascoded amplifier circuit.

Switched capacitor integrator system

A multimode voltage regulator includes a low current pass device and a high current pass device each adapted for connection between a power supply and a load; an error amplifier responsive to a difference between a reference voltage and a function of the voltage on the load to produce an error signal; and a low power driver responsive in a low load power mode to an error signal for operating the low current pass device to provide low power to the load and a high power driver responsive in a high load power mode to an error signal for operating the high current pass device to provide high power to the load for maintaining efficiency over high and low power load operation.

Multimode voltage regulator

A sigma-delta analog-to-digital converter includes an integrator having an input and an output and an integrator capacitor connected between the input and output. A switched-capacitor input circuit includes at least one input capacitor, an input sampling switching circuit and an input delivery switching circuit. The input sampling switching circuit includes at least one input sampling switch operable to connect the input capacitor to be charged by an input voltage at a sampling rate. The input delivery switching circuit includes at least one input delivery switch operable to connect the input capacitor to transfer charge to the integrator capacitor at a first transfer rate. A switched-capacitor feedback circuit is connected in a feedback path between the input and output of the integrator. The feedback circuit includes at least one feedback capacitor, a feedback sampling switching circuit and a feedback delivery switching circuit. The feedback sampling switching circuit includes at least one feedback sampling switch operable to connect the feedback capacitor to be charged by a feedback reference voltage at the sampling rate. The feedback delivery switching circuit includes at least one feedback delivery switch operable to connect the feedback capacitor to transfer charge to the integrator capacitor at a second transfer rate. The second transfer rate is a predetermined factor greater than the first transfer rate such that the sampled feedback reference voltage charge is transferred to the integrator capacitor at a greater rate than the transfer of the sampled input voltage charge to prevent modulator instability due to an input overload condition.

Switched-capacitor sigma-delta analog-to-digital converter with input

The dc-offset voltage of an amplifier is calibrated by: (1) configuring the amplifier as a comparator, (2) using the output of the comparator to drive the up/down select input of an up/down counter, and (3) using the output count of the up/down counter to control: (a) a dc-offset correction voltage being: (i) applied across the inputs of the amplifier, or (ii) being used to adjust a voltage which controls an operating parameter of a device in the amplifier, or (b) switches which selectively adjust the effective size or operating conditions of a transistor or other device such that the dc-offset voltage of the amplifier is adjusted corresponding to the value of the output count. At the end of a calibration cycle, the output count of the up/down counter is maintained and is used to: (a) control a voltage which is applied permanently in series with one of the inputs of the amplifier or to an operating parameter control lead of a device in the amplifier, or (b) maintain the position of switches used to adjust the effective size or operating conditions of the transistor or other device in the amplifier to compensate for the offset voltage thereof.

Calibrating the DC-offset of amplifiers

An insubstantial amount of noise results at the output of a circuit when an output of a primary amplifier is disconnected from and reconnected to the circuit in which is operating. The primary amplifier is placed temporarily in a muting configuration. A secondary amplifier permanently in a muting configuration is connected in parallel with the primary amplifier. The output of the primary amplifier then is disconnected from a circuit node to which it is attached. The primary amplifier may then be taken out of its muting configuration. After, for example, configuring the primary amplifier as a comparator and calibrating its dc-offset voltage, the primary amplifier is placed back into a muting configuration. The secondary amplifier then is disconnected from the primary amplifier. The primary amplifier may subsequently be taken out of muting configuration to resume its normal function in the circuit.

Switching amplifiers into and out of circuits with reduced output noise

A track-and-hold circuit that utilizes the negative of the input signal to improve tracking of the input signal during the track mode. By applying the negative of the input signal to an amplifier node to which the output signal is coupled, the output signal is forced to track the input signal in magnitude and polarity. Single-ended and fully differential embodiments of the circuit are disclosed, as well as embodiments using an operational amplifier and a cascode inverter amplifier. An improved switching scheme reduces delay in the transition from the hold mode to the track mode. A sample-and-hold circuit may be constructed from a pair of the track-and-hold circuits.

Track-and-hold circuit utilizing a negative of the input signal for

A circuit that provides samples of in-phase and quadrature components of an input waveform includes an oversampling ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.

In-phase and quadrature sampling circuit

Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Gain linearity correction circuit for MOS circuits

A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.

Double sampled biquad switched capacitor filter

A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.

Method for reducing errors in switched-capacitor digital-to-analog

Error reduction in switched capacitor digital-to-analog converter

A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.

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Dracut, MA, United States of America

Paul F Ferguson, Jr