Analog Devices,inc.

Mediatek Singapore Pte. Ltd.

Paul F Ferguson

Xavier S Haurie

Jeffrey Carl Gealow

Hae-Seung Harry Lee

Michael Anthony Ashburn, Jr

Gabriele Manganaro

Iuri Mehr

Thomas James Barber, Jr

Gabor C Temes

Lapoe E Lynn

Michael A Ashburn

Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

Limiting aging effects in analog differential circuits

An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.

Continuous-time oversampled converter having enhanced immunity to noise

A system and method including a DAC that receives a multi-bit digital signal and outputs at least two analog signals including a first analog signal and a second analog signal, the first analog signal being indicative of a sum of values of bits in the multi-bit digital signal, the second analog signal also being indicative of said sum of values of said bits in the multi-bit digital signal. The first and second analog signals may be substantially equal or they may be different from each other.

Method and apparatus for use in switched capacitor systems

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals Indicative of the digital signals to a signal conditioning stage at an output data rate different the input data mute.

An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.

Offset calibration system

A digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which integrates the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors store a binary representation of the digital input signal. The output circuit includes a zeroth order sample-and-hold circuit having first and second stages with respective first and second operational amplifiers. The first and second stages are cascaded together during a sample phase so that the analog output signal is stored in a capacitor in a feedback path between the output of the second stage and the input of the first stage, and are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.

Capacitor-based digital-to-analog converter with continuous time output

A method and system for high bandwidth, high gain offset compensation in a read channel integrated circuit includes zeroing the analog read signal applied to the signal path at a first location in the read channel integrated circuit path prior to a first amplifier which has a first gain and a first bandwidth magnitude characteristic with a high frequency boost; coupling a signal from the first amplifier to a second amplifier which has a second gain larger than the first and a second bandwidth magnitude characteristic having high frequency roll-off; and further coupling the signal further from the second amplifier to a storage device and feeding back the signal stored in the storage device to the first amplifier to apply the high frequency boost of the first bandwidth magnitude characteristic to compensate for the high frequency roll-off of the second bandwidth magnitude characteristic; decoupling the signal from the storage device and removing the zeroing of the analog read signal applied to the signal path.

Growing community of inventors

North Andover, MA, United States of America

Paul F Ferguson