Agere Systems Inc.

Lucent Technologies Inc.

Paul F Barnes

Donald Earl Hawk, Jr

Parag Madhani

Kandaswamy Prabakaran

Ramin Khoini-Poorfard

Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.

Systems and methods for supporting a subset of multiple interface types in a semiconductor device

Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die with at least two IO buffers. One of the IO buffers is located a distance from a particular package pin and another of the IO buffers is located a greater distance from the particular package pin. The IO buffer located closest to the package pin includes first bond pad electrically coupled to a circuit implementing a first interface type and a first floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type and a second floating bond pad. In some cases, the first floating bond pad is electrically coupled to the circuit implementing the second interface type via a metal layer wire, and the first floating bond pad is electrically coupled to the particular package pin.

Systems and methods for distributing I/O in a semiconductor device

An integrated circuit includes a string of substantially similarly-shaped resistive cells, each cell having a first resistive portion and a second resistive portion, the string having an overall orientation and at least one cell, preferably substantially all cells, and more preferably all cells have their respective centerlines oriented at non-orthogonal angles, preferably about 45 degrees, relative to the overall orientation. The cells are contiguous such that a resistor is formed by the first resistive portion of one cell and the second resistive portion of an adjacent cell. The cells preferably have a substantially hexagonal shape and are arranged into substrings. If the string includes a folding point, substrings immediately adjacent to the folding point should include an odd number, preferably three, of cells, and substrings not adjacent to the folding point should comprise an even number, preferably two, of cells. Preferably, the hexagonally shaped cells include two longer sides and four shorter sides, each cell having a tap substantially centrally positioned along one of its longer sides, a resistor being formed between the taps of any two adjacent cells. The taps are preferably arranged to form a grid such that each tap is aligned with at least one other tap substantially parallel to the overall orientation and each tap is aligned with at least one other tap substantially perpendicular to the overall orientation. A converter, such as a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC) includes such a resistor string.

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Coplay, PA, United States of America

Paul F Barnes