Texas Instruments Corporation

Paul Eric Landman

John William Fattaruso

Wai Lee

Patrick W Bosshart

Robert Floyd Payne

Woo Jin Kim

Keith Brouse

Lin Wu

Michael De Wit

Systems and methods are provided for providing a filtered, thermometer coded output signal from an N bit digital input, where N is an integer greater than one. A truncated lookup table provides a corresponding truncated thermometer code in response an address related to the N bit digital input. A code recovery assembly transforms the truncated thermometer code into a thermometer coded output according to a recovery bit associated with the N bit digital input.

System and method for providing a thermometer coded output filter

The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction componentperforms duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled bufferbuffers the differential pair of square wave signals and provides the buffered signals to a feedback circuitthat measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffercan also remove skew from the signals. In a transmitter, the buffered signals are also generally provided to a multiplexeror encoder and in a receiver, the buffered signals are also generally provided to a sampling component

Systems and methods of performing duty cycle control

A digitally-controlled oscillator (DCO) (), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO () is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (). Each of capacitors () has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger () that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic () that inverts the common node of the capacitors (). The switching time at the input of Schmitt trigger () depends upon the variable load presented by the array of switched capacitors (), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (). A digital phase-locked loop (PLL) clock generator circuit () including a phase detector (), digital loop filter () in combination with the DCO (), and a programmable frequency divider () providing a feedback path from the output of the DCO () to the phase detector (), is also disclosed. The PLL clock generator () may be used in an integrated circuit such as a digital signal processor () or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system ().

Digitally-controlled oscillator with switched-capacitor frequency selection

A domino logic circuit (,) comprising a first phase domino logic circuit (,) operable in a precharge phase and an evaluate phase. The first phase domino logic circuit comprises a precharge (,) node operable to change states. The domino logic circuit also comprises a second phase domino logic circuit (,) operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the first phase domino logic circuit are out of phase with respect to the precharge phase and an evaluate phase of the second phase domino logic circuit. Further, the second phase domino logic circuit comprises a precharge node (,) operable to change states in response to the states of the first phase domino logic circuit. Each of the first and second phase domino logic circuits further comprises a coupling device (,) which when conducting couples the precharge node to a precharge voltage during a precharge phase and a discharge path (,) corrected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase, wherein the discharge path comprises logic circuitry. The first phase domino logic circuit is operable such that the precharge node of the first phase domino logic circuit is charged to a first state during the precharge phase of the first phase domino logic circuit, and the precharge node of the first phase domino logic circuit conditionally changes to a second state during the evaluate phase of the first phase domino logic circuit. The second phase domino logic circuit is operable such that the state of the precharge node of the second phase domino logic circuit may change in the evaluate phase of the second phase domino logic circuit and in response to the first phase domino logic circuit only when the state of the precharge node of the first phase domino logic circuit did not change in an immediately preceding evaluate phase of the first phase domino logic circuit.

Inverting hold time latch circuits, systems, and methods

A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60). A digital phase-locked loop (PLL) clock generator circuit (50) including a phase detector (64), digital loop filter (62) in combination with the DCO (60), and a programmable frequency divider (66) providing a feedback path from the output of the DCO (60) to the phase detector (64), is also disclosed. The PLL clock generator (50) may be used in an integrated circuit such as a digital signal processor (30) or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system (200).

Growing community of inventors

Allen, TX, United States of America

Paul Eric Landman