International Business Machines Corporation

Paul Eric Dahlen

Gerald Keith Bartley

Philip Raymond Germann

Mark Owen Maxson

Darryl John Becker

Andrew Benson Maki

John Edward Sheets, Ii

John Michael Borkenhagen

Todd Alan Christensen

William Paul Hovis

Trevor Joseph Timpane

Layne A Berge

John Richard Dangler

Kent Harold Haselhorst

James Anthony Marcella

Robert Allen Drehmel

George Russell Zettles, Iv

Wayne Melvin Barrett

Daniel Ramirez

Timothy Joseph Schmerbeck

Kyle Schoneck

Thomas Donald Kidd

Roger John Gravrok

Miles Frank Swain

Douglas A Baska

Timothy Lindquist

Dennis Martin Rickert

Pat Rosno

Kenneth Claude Hinz

Carl-Otto Nilsen

Sierra Spring

David Loren Heckmann

Method, apparatus and computer program product for spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency response comprising acquiring a sample waveform including a set of discrete uniformly spaced samples from a target system, wherein the sample waveform is a time domain vector; applying FFT transforming the time domain vector into the frequency domain; analyzing the frequency domain response including calculating the magnitude response; and determining whether the sample waveform has spurs including comparing the magnitude response to an average noise floor threshold including determining that the magnitude response having an average noise floor value above the average noise floor threshold has one or more spurs and determining that the magnitude response having an average noise floor value below the average noise floor threshold has no spurs, wherein a spur indicates unaligned data having a delayed bit flip.

Spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency response

Surface mount device (SMD) placement to control a signal path in a printed circuit board (PCB), including: adding, to a PCB, a plurality of signal path segments, each signal path segment of the plurality of signal path segments ending at corresponding pad of a plurality of pads, wherein a first pad of the plurality of pads is couplable to a second pad of the plurality of pads to create a first signal path and is couplable to a third pad of the plurality of pads to create a second signal path; and coupling, via a discrete SMD, the first pad and the second pad to create the first signal path comprising a first signal path segment of the plurality of signal path segments and a second signal path segment of the plurality of signal path segments.

Surface mount device placement to control a signal path in a printed circuit board

Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Continuity check monitoring for microchip exploitation detection

Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process.

Signal quality monitoring to defeat microchip exploitation

A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Resistance sensing for defeating microchip exploitation

A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Doped implant monitoring for microchip tamper detection

A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip.

Enhanced architectural interconnect options enabled with flipped die on a multi-chip package

A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.

Method of enhancing on-chip inductance structure utilizing silicon through via technology

A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.

Implementing tamper evident and resistant detection through modulation of capacitance

An apparatus and method detect microchip tampering by including a capacitance circuit that comprises a protective cover. Dielectric material may be sandwiched between the cover and a backside metal layer, which may be proximate a protected surface of the microchip. Changes in the capacitance of the above circuit caused by alteration of the cover or other component of the capacitance circuit may be sensed and prompt defensive action.

Capacitance-based microchip exploitation detection

Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Implementing enhanced wiring capability for electronic laminate packages

A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design

Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically include metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Capacitance structures for defeating microchip tampering

A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.

Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory

A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.

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Rochester, MN, United States of America

Paul Eric Dahlen