Applied Micro Circuits Corporation

Paul Edward Vanderbilt

Joseph James Balardeta

Wei Fu

Sudhaker Reddy Anumula

Hongming An

Mehmet Mustafa Eker

Bruce H Coy

Allen Carl Merrill

Brian Lee Abernathy

Shyang Kye Kong

A system and method are provided for compensating a comparator threshold level. The method comprises: accepting an input signal with an ac component; lowpass filtering the input signal to generate the input signal average voltage; accepting the input signal average voltage; accepting a first dc level; summing the average voltage with the first dc level; supplying a first sum as a first comparator threshold level; comparing the input signal to the first comparator threshold level; and, supplying a first comparator output signal with an ac component. In some aspects of the method, accepting a first dc level includes accepting a plurality of dc levels. Then, the average voltage is summed with each of the plurality of dc levels and supplied as a corresponding plurality of comparator threshold levels. The input signal is compared to each of the comparator threshold levels and a plurality of comparator output signals are supplied.

System and method for comparator threshold adjustment

A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.

Configurable triple phase-locked loop circuit and method

A configurable multiplexing circuit and arrangement suited for phase locked loop applications. The multiplexing circuit includes an EX-OR element, a multiplexer element and a summer element. Each element is configured for receiving a particular type of detection signal output, as an input for one of multiple selectable multiplexing operations. The multiplexing circuit further includes a selection signal input, coupled to the EX-OR element, the multiplexer element and the summer element, for receiving a selection signal that enables one or more of the EX-OR element, the multiplexer element, and the summer element. Non-enabled elements are powered down to eliminate jitter and performance penalties.

Configurable multiplexing circuit and method

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Encinitas, CA, United States of America

Paul Edward Vanderbilt