International Business Machines Corporation

Western Digital Technologies, Inc.

Paul Edward Movall

Daniel Frank Moertl

Charles Scott Graham

Shawn Michael Lambeth

David R Engebretsen

William Joseph Armstrong

Gregory Michael Nordstrom

Josep Cors

Eric G Thiemann

Thomas R Sand

Claude Basso

Colin Beaton Verrilli

Bruce Marshall Walk

Eric John Nelson

Thomas James Osten

Ward Ray Nelson

Daniel Mark Hursh

David Lee Dosch

Stephanie Maria Forsman

Brett J Reese

Paul Saby Halverson

Grady W Jensen

David Robison Hall

Patrick Allen Buckland

Stephen Peter Mroz

Chetan Mehta

John Steven Langford

Henry Joseph May

Ellen Marie Bauman

Gary Dean Anderson

Brent William Jacobs

Neil Clair Berglund

Scott E Burton

David George Lund

Michael Youhour Lim

Daniel Robert Lipps

Kevin Gene Kehne

Gerald Kreissig

Andreas Arnez

Brian Gerard Holthaus

Thomas Joseph Warne

Shaun Allan Wetzstein

Daniel Paul Wetzel

Joshua W Boyer

Clinton Gene Laschkewitsch

William Joseph Armstrong, Jr

Curtis Adam Harper

Nancy Marie Uthke-Schmucki

Paul John Johnsen

A data storage device is disclosed comprising a head actuated over a disk. The disk is spun at a first speed while writing first data to the disk based on a first disk format defining a first capacity for the disk. When a command is received from a host to spin the disk at a second speed different from the first speed, the disk is spun at the second speed while writing second data to the disk based on a second disk format defining a second capacity for the disk different from the first capacity.

Data storage device operated at different spin speeds

A method may receive, at a first node, a first message with a first message data structure from a second node. The first message data structure may include a counter for each resource of a plurality of resources that is indicative of a most current age of a master copy of the resource known by the second node. The first node may include a current data structure with a counter for each resource that is indicative of a most current age of the master copy of the resource known by the first node. The method may determine whether at least one counter in the current data structure is older than the corresponding counter in the message data structure. The method may update the counter that is older, e.g., to learn the most current age of the master copy of the resource known by the second node, based on the determination.

Utilization of data structures to synchronize copies of a resource

A method includes receiving firmware at a network entity and determining whether the network entity is to operate as a controlling Fiber Channel forwarder based on the firmware.

Configuration of network entities using firmware

Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer, at least one packet interface, and an analysis assist layer. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis assist layer analyzes the packet to determine a reason code to assign to the packet. The analysis and bifurcation layer then analyzes the packet based at least in part on the reason code.

Packet routing with analysis assist for embedded applications sharing a single network interface over multiple virtual networks

A method of managing a database may include, at a node, assigning a pre-assimilation value to a hardware instance identifier of a hardware component before the node is assimilated into a multi-node computing system. The method may also include receiving a post-assimilation value after the node has been assimilated into the multi-node computing system. The method may also include updating the pre-assimilation value with the post-assimilation value.

Pre-assimilation values and post-assimilation values in hardware instance identifiers

Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer and at least one packet interface. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis and bifurcation layer analyzes the packet and sends the packet to the packet interface, which then routes the packet to the first application.

Packet routing for embedded applications sharing a single network interface over multiple virtual networks

An approach is described for managing error logs and corresponding error descriptors among a plurality of controller nodes of a distributed network fabric. According to such approach, an error log may include output from a runtime code trace. The runtime code trace may include storing trace statements from a currently running process in one or more of a plurality of trace buffers. The trace buffers may be memory-mapped circular buffers. Additionally, an error descriptor may be created from the error log. A globally unique identifier may be assigned to the error descriptor, and both the error descriptor and the globally unique identifier may be broadcast to each other controller node among the plurality of controller nodes.

Managing error logs in a distributed network fabric

Distributed event management in an embedded support processor computer system includes an embedded support processor having an event distribution agent used to communicate with local processes internal to the embedded support processor. A process communicates with the event distribution agent of the embedded support processor and registers for one or more events. Another process signals an event to the event distribution agent of the embedded support processor. The event distribution agent of the embedded support processor notifies each registered process of the signaled event. The event distribution agent of the embedded support processor is used to communicate with a peer event distribution agent included in a main processor of the embedded support processor computer system, and to communicate over a network with a peer event distribution agent included in an attached device, such as a personal computer.

Method and apparatus for implementing distributed event management in an embedded support processor computer system

A recovery process for embedded processors monitors other processes in the system. Each process may specify a recovery policy residing in nonvolatile electronic memory that preferably includes a recovery count, a recovery time, and a recovery action. If a process terminates unexpectedly, the recovery process determines whether the process had a corresponding recovery policy. If not, the recovery process does not recover the process. If the process has a corresponding recovery policy, the recovery process determines whether it can recover the process by examining the recovery count and recovery time specified in the recovery policy. If the process can be recovered, the recovery process performs the recovery action specified in the corresponding recovery policy. If the process cannot be recovered, the recovery process resets the system. In this manner, a single process may be recovered by the recovery process without user intervention and without affecting other processes running on the system, and without performing a reset of the entire system.

Apparatus and method for process recovery in an embedded processor system

A method, apparatus, and computer instructions for determining validity of and updating a microcode image. Responsive to initiation of an update process, a first validity indicator is checked to determine whether a first microcode image in the memory is valid. In response to the first microcode image being valid, a second validity indicator is set indies, to indicate that a second microcode image is invalid, and the update process is allowed to update the second microcode image to form an updated microcode image. A determination is made as to whether the updated microcode image is valid. The second validity indicator is set to indicate that the updated microcode is valid if the updated image is valid. The second validity indicator is checked during booting of a data processing system. If the second validity indicator is valid, the updated microcode will be loaded.

Method and apparatus for updating a microcode image in a memory

A method and apparatus are provided for abstraction of a physical hardware implementation to logical software drivers. An operating system kernel includes a device driver layer, an enhanced I/O abstraction layer and physical hardware implementation details layer. The physical hardware implementation details layer encapsulates hardware details for the physical hardware implementation. The enhanced I/O abstraction layer abstracts the hardware details for the device driver layer and creates unique logical I/O device structures for each embedded function in the physical hardware implementation. By using the enhanced I/O abstraction layer, device drivers maintain their independence from the physical hardware implementation. Using the enhanced I/O abstraction layer also enables a single driver with one binary image to support embedded functions spread out across multiple chip implementations, and multiple instances of an embedded function on one or multiple chips.

Method and apparatus for abstraction of physical hardware implementation to logical software drivers

A method, system, and apparatus for reestablishing communications between a host and a service processor after the service processor has ceased to function correctly is provided. In one embodiment, the host exchanges heartbeat signals with the service processor. The heartbeat signals indicate that the service processor is active and functioning. In response to a failure to receive a heartbeat signal or in response to some other indication that the service processor is not performing correctly, the host causes a hard reset of the service processor. In addition, the service processor can detect a failure within itself and initiate a hard reset to itself. After the hard reset, the service processor returns to a monitoring mode without performing initial tests of the data processing system. Furthermore, the data processing system remains active and is not shut down during the hard reset of the service processor.

Service processor reset/reload

Growing community of inventors

Rochester, MN, United States of America

Paul Edward Movall