Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Paul Edward Kitchin

Karthik Sundaram

Rama S Gopal

Alexander J Branover

William Louie Walker

Andrew William Lueck

David A Kaplan

Ronald Perez

Steven Kommrusch

Tarun Nakra

Sonu Arora

Nicholas Humphries

Brian C Grayson

Ryan J Hensley

Hao Wang

Krishna Sai Bernucho

Gerald Zuraski

Ken Yu Lim

A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

Memory load to load fusing

A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.

Register renaming of a shareable instruction operand cache

According to one general aspect, an apparatus may include a first cache configured to store data. The apparatus may include a second cache configured to, in response to a fill request, supply the first cache with data, and an incoming fill signal. The apparatus may also include an execution circuit configured to, via a load request, retrieve data from the first cache. The first cache may be configured to: derive, from the incoming fill signal, address and timing information associated with the fill request, and based, at least partially, upon the address and timing information, schedule the load request to attempt to avoid a load-fill conflict.

Method to avoid cache access conflict between load and fill

According to one general aspect, an apparatus may include a branch prediction unit, a fetch unit, and a pre-fetch circuit or unit. The branch prediction unit may be configured to output a predicted instruction. The fetch unit may be configured to fetch a next instruction from a cache memory. The pre-fetcher circuit may be configured to pre-fetch a previously predicted instruction into the cache memory based upon a relationship between the predicted instruction and the next instruction.

Instruction prefetcher dynamically controlled by readily available prefetcher accuracy

According to one general aspect, a load unit may include a load circuit configured to load at least one piece of data from a memory. The load unit may include an alignment circuit configured to align the data to generate an aligned data. The load unit may also include a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand. Wherein the load unit is configured to, if an active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.

Memory load and arithmetic load unit (ALU) fusing

A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.

Methods and apparatus related to processor sleep states

Methods, integrated circuit devices, and fabrication processes relating to power management transitions of a compute unit comprising a cache are presented. One method includes, responsive to an indication that the compute unit is attempting to enter a low power state, detecting at least one line of the cache differing from the corresponding line in memory, writing differing data from the at least one differing line to the memory, flushing at least one remaining differing line of the cache, and permitting the compute unit to enter the low power state, wherein the detecting and the writing are performed at a first frequency prior to the indication and at a second frequency subsequent the indication, and the second frequency is higher than the first frequency.

Accelerated cache rinse when preparing a power state transition

Dynamically predicting a Read-After-Write (RAW) hazard by employing a variable confidence score attributed to a RAW Resynchronization Predictor (RRP) for sampling the RRP at timing periods dynamically adjusted based on the confidence score to optimize prediction of the RAW hazard.

Read-after-write hazard predictor employing confidence and sampling

According to one general aspect, an apparatus may include an instruction fetch unit, an execution unit, and a cache resynchronization predictor, as described above. The instruction fetch unit may be configured to issue a first memory read operation to a memory address, and a first memory write operation to the memory address, wherein the first memory read operation is stored at an instruction address. The execution unit may be configured to execute the first memory read operation, wherein the execution of the first memory read operation causes a resynchronization exception. The cache resynchronization predictor may be configured to associate the instruction address with a resynchronization exception, and determine if a memory read operation stored at the instruction address comprises a resynchronization predicted store.

Method and apparatus for handling processor read-after-write hazards with cache misses

Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory.

Reintialization of a processing system from volatile memory upon resuming from a low-power state

We report methods, integrated circuit devices, and fabrication processes relating to power management transitions of multiple compute units sharing a cache. One method includes indicating that a first compute unit of a plurality of compute units of an integrated circuit device is attempting to enter a low power state, determining if the first compute unit is the only compute unit of the plurality in a normal power state, and in response to determining the first compute unit is the only compute unit in the normal power state: saving a state of a shared cache unit of the integrated circuit device, flushing at least a portion of a cache of the shared cache unit, repeating the flushing until either a second compute unit exits the low power state or the cache is completely flushed, and permitting the first compute unit to enter the low power state.

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Austin, TX, United States of America

Paul Edward Kitchin