Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Paul Edward Hanham

David Malcolm Symons

Francesco Giorgio

Neil Buxton

Julien Margetts

Shigehiro Asano

Jonghyeon Kim

Senthilkumar Diraviam

Josh Bowman

Matthew Stephens

Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

Method and system for buffer allocation management for a memory device

Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp. Example implementations also include a device operably coupled to a memory array, and with a memory controller device configured to receive a host command identifier associated with a host command, and configured to determine a device command associated with the host command and a memory controller device, and a debug record generator device operatively coupled to the memory controller device and configured to receive a device command timestamp corresponding to a time of the determined device command, and configured to determine a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.

Device and method for high performance memory debug record generation and management

Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By 'interleaving' and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Efficient decoding of n-dimensional error correction codes

There is provided a method of providing adjusted LLR values of a plurality of bits in a codeword to an LDPC decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory. The method comprises storing in a non-volatile memory controller associated with the non-volatile memory LLR values of the plurality of bits. The controller then determines a plurality of levels of the charge states represented by the plurality of bits. The controller then generates, by a distribution processor, distributions of a population of the plurality of bits in the codeword at each of the plurality of levels at a first and a second time after the first time. The controller then generates the adjusted LLR values based on a comparison between the first and second distributions, and then decodes the codeword according to the adjusted LLR values.

Non volatile memory controller device and method for adjustment

Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Pooled frontline ECC decoders in memory systems

A method for fast calculation of a frame error rate (FER) of an error correcting code (ECC) soft decoder using a soft read process includes determining an MI-FER conversion data structure based on a relationship between mutual information (MI) of input channels and output channels of a memory, and FER of the ECC soft decoder, and decoding an encoded data codeword stored in a memory page of the memory and read using a soft read process. The method further includes generating a set of joint probability values using the information from the soft read process and data indicating true bit values for the data codeword, determining an MI value using the set of joint probability values, and determining an FER estimate using the MI-FER conversion data structure.

System and method for improved memory error rate estimation

A system for an Error Correction Code ('ECC') decoder includes a first decoder and a second decoder. The first decoder is configured to determine a first estimated number of errors in encoded data received at the first decoder and to compare the first estimated number of errors to a first threshold and a second threshold. The second decoder is configured to receive the encoded data when the first estimated number of errors is below the first threshold and is above a second threshold. When the first estimated number of errors is above the first threshold, the first decoder passes the encoded data out of the ECC. The first decoder has a lower power consumption than the second decoder.

Low power error correcting code (ECC) system

A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.

Optimal LDPC bit flip decision

A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.

Low BER hard-decision LDPC decoder

A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.

Soft decision LDPC decoder with improved LLR from neighboring bits

A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.

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Froxfield, United Kingdom

Paul Edward Hanham