Fairchild Semiconductor Corporation

Paul E Riley

Alan B Ray

Paul Bayer

A method for planarizing an insulating layer overlying an irregular topographic substrate, e.g., a conductive layer, is planarized by use of a sacrificial planarization layer. The planarization layer is removed using an oxygen-containing plasma generated in a parallel electrode reactor operating at a low excitation frequency and high pressure. Once the interface between the planarization layer and the conductive layer is reached, a second plasma with a reduced oxygen content is employed to avoid overetching the planarization layer. It has been observed that oxidizing species liberated during the etching of the insulating layer, typically silicon dioxide, contribute to the oxidation and hence removal of the planarization layer. The process may be monitored by observing the spectral emissions from species generated or consumed during planarization or by changes in the optical interference pattern, allowing termination of the etch at the proper time to avoid over-etching and under-etching of the insulating layer.

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San Jose, CA, United States of America

Paul E Riley