Gte Laboratories Incorporated

Paul E Poppert

Marvin J Tabasky

Eugene O Degenkolb

Jeremiah P McCarthy

Ernest A Goldman

Method of producing metal interconnections in a semiconductor integrated circuit structure of a body of silicon coated with silicon dioxide having openings therein exposing contact regions to underlying silicon. A thick layer of an insulating or dielectric material, for example, polymide, is deposited on the body. Grooves in the pattern of the desired interconnections are etched through the thick insulating layer to the underlying silicon dioxide and contact regions. Metal is deposited to fill the grooves and cover the thick layer of insulating material. Excess metal is removed to form a planar surface exposing the surface of the thick insulating layer with the grooves containing metal to provide electrical connections between contact regions.

Method of producing interconnections in a semiconductor integrated

Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.

Method of producing integrated circuit structures

Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.

Monolithic CMOS integrated circuit structure with isolation grooves

Monolithic integrated circuit structure and method of fabrication

A body of silicon has sectors of N-type and P-type covered by silicon oxide gate layers with adjacent regions covered by a thicker silicon oxide field layer. Gate members of N-type polycrystalline silicon are placed on the gate layers to define an N-type channel region in the N-type sector and a P-type channel region is the P-type sector. P-type conductivity imparting material is introduced into the remaining regions of the N-type sector to convert them to P-type source/drain regions with an intervening N-type channel region, and N-type conductivity imparting material is introduced into the remaining regions of the P-type sector to convert them to N-type source/drain regions with an intervening P-type channel region. The exposed silicon oxide is grown to a thicker field layer and a protective oxide is formed on the polycrystalline gate members. The source/drain regions are exposed and adherent contact members of polycrystalline silicon of N and P-type are formed in ohmic contact with the source/drain regions of N and P-type, respectively. The surfaces of the polycrystalline contact members are metallized thereby shorting out rectifying junctions between N and P-type contact members.

Method of fabrication of monolithic integrated circuit structure

Method of fabricating a monolithic integrated circuit structure incorporating complementary metal-oxide-silicon field effect transistors (CMOS FET's) including providing a body of silicon produced by conventional techniques having a sector of N-type and a sector of P-type each covered by a thin silicon oxide layer and a thin silicon nitride layer. The regions of the body adjacent to each of the sectors are covered by a thicker silicon oxide field layer. Portions of the thin nitride and oxide layers are removed to expose spaced apart zones in each of the sectors. Adherent contact members of low resistivity polycrystalline silicon of N and P-type conductivity are formed in contact with the exposed surfaces of the zone in the P and N-type sectors, respectively. Where N and P-type contact members are contiguous a rectifying junction is produced. The surfaces of the polycrystalline contact members are metallized with a highly conductive material, thereby shorting out the rectifying junctions. P-type conductivity imparting material is implanted through a gate oxide layer into the N-type sector except the portion shielded by a first gate electrode and the contact members. N-type conductivity imparting material is implanted through a gate oxide layer into the P-type sector except the portions shielded by a second gate electrode and the contact members. The body is heated to drive the implanted conductivity type imparting materials further into the sectors and to diffuse conductivity type imparting material from the contact members into the adjacent zones.

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Acton, MA, United States of America

Paul E Poppert