Honeywell G.m.b.h.

Paul E Knight

Paul J Short

Thomas A Weingartner

Jennifer A Graves

A display memory system consisting of a controller and a display memory that has a read display memory cycle time that is a non-integer multiple of the write display memory update rate. The display memory being partitioned into two frames of display memory with each frame having a plurality of subframes. The controller consisting of a read display memory decoder, a read display memory next subframe generator a read display memory latch and consisting of a write display memory decoder, a write display memory next subframe generator and write display memory latch.

Growing community of inventors

Streamwood, IL, United States of America

Paul E Knight