Nec Electronics Corporation

Nec Electronics America, Inc.

Paul E Cohen

Jason Peng

Tetsu Koyama

Ioannis S Dedes

An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the 'most likely' path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the 'most likely' sequence of convolutionally-encoded symbols received by the decoder.

Apparatus and method for implementing a decoder for convolutionally encoded symbols

A multidimensional equalizer and cross talk canceller for a communication network that simultaneously removes far end cross talk NEXT) and intersymbol interference (ISI) from a received signal. A multidimensional-pair channel is treated as a single multidimensional channel and a receiver in the communication network equalizes received signals through the use of the multidimensional equalizer. A decision feedback equalizer determines a multidimensional steepest descent gradient to adjust matrix coefficients.

Four dimensional equalizer and far-end cross talk canceler in Gigabit Ethernet signals

In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A.new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the &ldquo;most likely&rdquo; path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the &ldquo;most likely&rdquo; sequence of convolutionally-encoded symbols received by the decoder. The convolutional decoding can be implemented with a digital signal processor and a dedicated peripheral unit. This apparatus can provide an efficient use of memory for the possible decoding paths.

Digital signal processor decoding of convolutionally encoded symbols

In a data processing system, the ability to provide indirect addressing capability is implemented by providing a peripheral system having a first memory unit, second memory unit, and a control unit. In a first embodiment of the invention, a first address signal applied to the control unit accesses a first location in the first memory unit. The signal group stored in the first location is a first address signal group. The first signal group is used by the control unit to access a second location in the second memory unit. The access of the second location can be used to store a data signal group therein in a write operation or can be used to retrieve a data signal group therefrom in a read operation. In the second embodiment of the invention, the control unit includes a pointer unit responsive to a plurality of control address signal groups. The control address signal groups cause the storage or retrieval of data signal groups in a data register in the control unit. The address signal group in the address register can be stored therein by an associated processing unit. The control address signal groups also determine a next address in an address register. The control unit uses the address signal group in the address register to determine an address signal group in a first location in the first memory unit. The address signal group in the first location is used to access a second location in the second memory unit. This access of the second location permits data signal groups to be transferred from the data register in the control unit to the second location or data signal groups to be transferred from the second location to the data register.

Apparatus and method for a random access peripheral unit

An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the &ldquo;most likely&rdquo; path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the &ldquo;most likely&rdquo; sequence of convolutionally-encoded symbols received by the decoder.

A data processing system for use in arrays includes a digital signal processor, a search accelerator unit and memory unit, the memory unit having a group storage locations that store the data entries of the matrix. The locations in the matrix are identified by the indices of the location. The access of the matrix by the digital processing unit typically includes an access to a series of locations at periodic intervals along a row or diagonal of the matrix. The series of data entries can include a sequence of non-neighboring matrix data entries. The search accelerator unit includes at least one pointer unit. The pointer unit in the search accelerator unit receives beginning array indices identifying the array entry. The pointer unit increments the array indices to provide the sequence of data entry indices for the matrix. The data entry array indices are converted to a series of memory location addresses. By using the search accelerator unit to provide the resulting series of memory location addresses, the digital signal processor is relieved of developing a series of non-regular addresses for memory locations. The search accelerator unit can include a size register that determines the size of the matrix to be searched and determines the increment used in searching the matrix. The invention is applied to the processing of speech signals using codebook matrices.

Apparatus and method for an array processing accelerator for a digital signal processor

A device that broadcasts an electronic serial number, or ESN, is made secure from cloning using one or more of a plurality of measures, including coupling the memory used for storing the ESN more closely to the ESN processor, fabricating the ESN memory as part of the ESN processor, including the ESN memory in another processor and encrypting communications between the other processor and the ESN processor, and comparing multiple copies of the ESN stored in different memories. The later technique is also effective in securing the JTAG port of an ESN processor.

Security for a mobile or personal communications device having an

A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field operations. Additionally, such a system advantageously provides a processor which does not include an original bit field instruction set with the ability of performing bit field operations. Such a system also advantageously avoids difficulties involved in encoding bit field instructions.

Bit-field peripheral

A discrete cosine transform engine is disclosed. The engine receives an input matrix of data and provides a transformed matrix of data, the input matrix and the output matrix each having a plurality of row locations and a plurality of column locations. The engine includes a plurality of input accumulators and a plurality of output accumulators. The plurality of input accumulators accumulate data from the input matrix of data in parallel to provide a plurality of transform coefficient outputs. A digital signal processor receives the plurality of transform coefficients, multiplies the transform coefficients by a plurality of transform constants and provides a plurality of transform products. Each output accumulator receives the transform products and accumulates the products to provide the transformed matrix of data.

DCT peripheral for a digital signal processor

A discrete cosine transform engine which receives an input matrix of data and provides a transformed matrix of data, the input matrix and the output matrix each having a plurality of row locations and a plurality of column locations. The engine includes a plurality of input accumulators, a plurality of multiplication circuits and a plurality of output accumulators. The plurality of accumulators accumulate data from the input matrix of data in parallel to provide a plurality of transform coefficient outputs. The plurality of multiplication circuits receive the plurality of coefficient outputs and multiply the coefficient outputs by transform constants to provide a plurality of transform products. Each output accumulator receives the transform products and accumulates the products to provide the transformed matrix of data.

Highly parallel discrete cosine transform engine

A means for precisely identifying the location of an error in a computer program executing in a microprocessor is provided by an instruction complete counter circuit that counts each of the program instructions completed by the microprocessor up to the time of an error in execution.

Growing community of inventors

San Jose, CA, United States of America

Paul E Cohen