Adtran Gmbh

Paul E Calvert

Robert Scott Appleton

Andrew L Plankenhorn

Steven Creg Killen

A bit error rate test (BERT) system is configured as a field programmable gate array that emulates multiple independent BERT generators. The BERT generators produce test frames containing test pattern codes associated with respectively different time division multiplexed (TDM) digital communication channels, that are not necessarily mutually contiguous within a plurality of TDM timeslots of a network communication frame serving digital communication circuits. A framing unit assembles the test code patterns into a test frame and transmits the test frame over a serial network interface to a plurality of digital channel units of a channel bank. The framing unit also interfaces contents of test code patterns within test frames returned from the channel units over the serial network interface with a plurality of data channel-specific virtual BERT receivers, associated with respective digital communication channels. A bit error processor determines errors in the contents of the test code patterns within returned test frames.

Growing community of inventors

Lacey's Spring, AL, United States of America

Paul E Calvert