Sun Microsystems, Inc.

Oracle America, Inc.

Paul Durrant

Jeremy Graham Harris

Sunay Tripathi

Nicolas G Droux

Stephen Richard Hanson

David S Gordon

Yuzo Watanabe

Hossein Moiin

A method for configuring a link aggregation module, including configuring the link aggregation module to use an initial network interface card (NIC) selection algorithm, servicing a first plurality of packets using a plurality of NICs in an aggregation group, wherein the initial NIC selection algorithm is used to select the one of the plurality of NICs to service at least one of the first plurality of packets, collecting a plurality of first packet distribution statistics for the aggregation group corresponding to the servicing of the first plurality of packets, and selecting a first alternate NIC selection algorithm based on the plurality of first packet distribution statistics.

Method and apparatus for adaptive selection of algorithms to load and spread traffic on an aggregation of network interface cards

In general, in one aspect, the invention relates to a network interface card (NIC) aggregation framework, including a plurality of providers each configured to publish at least one port, a MAC client configured to send a packet to the at least one port, and a media access control (MAC) service module configured to map the at least one port to one of the plurality of providers, wherein the MAC service module comprises a client interface configured to interface with the MAC client and a provider interface configured to interface with each of the plurality of providers.

Network interface card aggregation framework

A method for obtaining a capability of a network interface card (NIC). The method includes sending a first data link provider interface (DLPI) request to the NIC and sending a DLPI acknowledgement to an operating system, where the DLPI acknowledgement includes the capability of the NIC. The method further includes enabling the capability on the operating system and establishing a direct communication channel between the NIC and the operating system using the capability.

Method and system for using DLPI to negotiate advanced interfaces

A method for processing a chain of packets involving obtaining the chain of packets from a network, obtaining destination information from a first packet in the chain of packets, determining whether destination information of the first packet matches destination information of a second packet in the chain of packets, aggregating the first packet and the second packet to obtain an aggregated chain of packets, if destination information of the second packet matches the destination information of the first packet, hashing destination information to obtain a hash value, and forwarding the aggregated chain of packets to at least one client using the hash value.

Method and system for handling received packets

A method for managing virtual memory including placing a first virtual memory page in a physical memory page to create a virtual-to-physical memory mapping, associating a first page mapping cookie value with the virtual-to-physical memory mapping, determining whether the virtual-to-physical memory mapping is valid using the first page mapping cookie value, and performing a memory operation addressing the first virtual memory page if the virtual-to-physical memory mapping is valid.

Page mapping cookies

In a computer processing apparatus, when writing data to, and/or reading data from, memory, one or more instruction bits are associated with the memory address for the data to specify how encryption or decryption is to be performed. The bit(s) may be part of the memory address or separate therefrom, for example as a data header. Multiple data paths provided to write data to, and read data from, memory. On at least one of the paths is hardware operable to perform encryption or decryption. Preferably at least one path is a non-encryption/decryption path. The path to be used to write the data to, or read the data from, memory is chosen in accordance with the instruction bits associated with the memory address.

Data encryption and decryption

A device driver (GRAPHICS, NETWORK, HIO, IOL, SERIAL) for use in a computer system comprising a processor (P), memory (M) and a device (GRAPHICS, NETWORK, HIO, IOL, SERIAL) operatively coupled to the computer system, the device driver being operable to control the device to monitor an operational status of the device, and consequent upon a change in the operational status to generate a fault report data indicating whether the change of status was caused internally within the device or externally by another connected device which caused the change of operational status to occur. The fault reports may also include an indication of the operational status of the device. Furthermore, if the fault report data indicates that the change of status was caused externally, the device driver may generate fault direction information indicative of an apparent direction on a connection between the device and the other device suspected as causing the indicated external fault. By providing an indication as to whether a fault has occurred internally or externally, and if externally, a relative direction on a data path from which the fault is perceived, a fault response processor can estimate the location of a faulty device of the computer system with improved accuracy.

Device drivers configured to monitor device status

A method and mechanism for generating a snapshot in a computing system. On initiating a snapshot of a first storage, the content of a portion of the first storage that includes at least one block is copying to snapshot storage and a copied indication for each copied block is recording in a copy map. Responsive to any write request to a block for which no copied indication has been recorded in the copy map, the content of the block is copied to the snapshot storage, prior to writing to that block. The content of other blocks for which no copied indication has been recorded in the copy map is successively copied to the snapshot storage. A copied indication for each copied block is recorded in the copy map. The successive copying can be performed as a background task.

Method and mechanism for generating a live snapshot in a computing system

A computer system compnses a processor (), memory () and a plurality of devices (), the processor () and the memory () being operable to effect the operation of a fault response processor (AFR), and a device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices. The fault response processor (AFR) is operable to generate a model which represents the processor (), the memory () and the devices () of the computer system and the inter-connection of the processor (), memory () and the devices (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL). The device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices () is arranged, consequent upon a change of operational status of the device, to generate fault report data indicating whether the change of status was caused internally within the device or externally by another connected device. The devices of the computer system may be formed as a plurality of Field Replaceable Units (FRU). The fault response processor (AFR) is operable, consequent upon receipt of the fault reports from the device drivers (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) to estimate the location of a FRU containing a faulty device by applying the fault indication to the model. In other embodiments the fault report data includes direction information indicating a connection between the device and the other connected device which caused the external fault. Having identified the faulty device the FRU may be replaced, thereby minimizing down time of the computer system.

Method and apparatus for locating a faulty device in a computer system

Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. A resource access controller controls access to resources addressed by at least one central processing unit. The resource access controller includes an address translation mechanism providing fake response identification as to whether or not a response is to be faked. The resource access controller also includes a fake response generator for selectively generating a faked response where the fake response identification of the corresponding translation entry indicates that a response is to be faked. The resource access controller is able to associate fake response indications with a resource and to generate a fake response when an attempt is made to access a resource labeled such that a faked response should be returned. The resource access controller can form part of a bridge that interconnects a first bus connected to a processor of the computer system, which processor includes at least one said central processing unit, and at least a second bus. However, the resource access controller can be provided at other points in a computer system where an address translation is performed, for example in a memory management unit.

Bus bridge resource access controller

A memory controller controls access to one or more memory units. The memory controller includes access control logic operable to receive a memory access request that references at least one memory address. It further includes a fake response record operable to record a fake response indication for an address for which a response is to be faked. The access control logic is operable on receipt of a memory access request to access the fake response record and to fake a response where a fake response indication for an address indicates that a response is to be faked. By providing such a faked response, an embodiment of the invention is able avoid multiple exceptions for the same memory location in a CPU. Also, by providing such a faked response, multiple bus errors for a memory location can also be avoided where a bus supports Direct Memory Access (DMA). The memory controller can be implemented in an integrated circuit. It can form part of a memory subsystem including the memory controller and at least one memory unit in an integrated circuit.

Memory access controller with response faking

To provide efficient resource access control in a computer system, a trap handler for handling a trap in the event of a faulty resource access being detected is arranged to define a diversion for subsequent access attempts to the same resource. An address translation mechanism is responsive to indication of a diversion for a resource access to modify an address mapping, whereby subsequent attempts to access the resource are diverted in accordance with the diversion. The trap handler can be arranged in a conventional manner to process an exception of the first faulty access to the resource. However, by defining the diversion, which can be used to map further attempts to access the same resource, unnecessary exception processing can be avoided.

Multiple traps after faulty access to a resource

Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. The resource can be a memory location, a peripheral or any other addressable system component. A resource access mechanism in a processor controls access to resources. The resource access mechanism includes an address control mechanism having a plurality of address control entries, each address control entry providing fake response identification indicating whether or not a response for the corresponding address is to be faked. The resource access mechanism also includes a fake response generator for selectively generating a faked response for an address in response to the fake response identification of the corresponding address control entry indicating that a response is to be faked.

Processor resource access control with response faking

A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

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Slough, United Kingdom

Paul Durrant