Agilent Technologies, Inc.

Paul Douglas Nuber

M Jason Welch

Victoria Meier

Dan Stotz

Guy Harlan Humphrey

Gayvin E Stong

Richard Alan Krzyzkowski

Jeffrey Thomas Robertson

C Stephen Dondale

Stephen E Clarke

At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

Method and apparatus for ensuring signal integrity in a latch array

A method of generating an IC design comprises the steps of generating an intermediate routing result to define interconnects between functional blocks on an IC. The next step is defining one or more repeater ranches in an interstice of the IC and generating a repeater placement plan for placement of repeater elements according to the repeater ranch boundary constraints. The process continues with the step of generating a final routing result to define interconnects between functional blocks that interconnect the repeater elements according to the repeater placement plan.

Process and system for repeater insertion in an IC design

An apparatus and method are provided for preventing buffers used to reduce delays on long lines of an IC from being damaged due to charge that collects on the buffers during manufacturing. In accordance with the present invention, a protection diode is included directly in at least each buffer that is used for this purpose, i.e., for the purpose of preventing delays on long lines of the IC. By including a protection diode in at least each buffer that is used for this purpose, the present invention obviates the need for having to use tools during the IC design process to determine a suitable location for a protection diode.

Method and apparatus for preventing buffers from being damaged by electrical charges collected on lines connected to the buffers

The present invention relates to a method of integrated circuit construction in which misaligned ports are linked via an alignment link made up of a wiring trace and signal buffer. The signal buffer and wiring trace are located within a common area of integrated circuit real estate.

Method of integrated circuit construction with port alignment and timing signal buffering within a common area

Localizing bypass capacitance for the purpose of reducing or eliminating noise in power supplies in an integrated circuit (IC). After a data path block of macro cells has been constructed by the IC designer, a determination is made as to which cells of the macro cells comprise functionality that will not be used by the IC when it is operating. At least a plurality of cells that are determined to be cells that comprise functionality that will not be used when the IC is operating are filled with bypass capacitors. Because there are typically a large number of cells that will not be used when the IC is operating, filling a plurality or all of these cells with bypass capacitors ensures that bypass capacitors will be located in close proximity to power supplies on the IC, which ensures that the bypass capacitors will be effective at reducing or eliminating noise in the power supplies.

Bypass capacitance localization

Programmable circuit blocks and programmable interconnection blocks are utilized to effectively modify the functionality of a section of the IC. The use of a fixed ion beam machine or similar device is unnecessary, allowing functional modifications of the IC by way of electrically programming the device. As a result, the IC designer is not limited in the number of ICs that may be modified, which facilitates faster testing of IC design changes. Also, an IC may be modified multiple times by simply reprogramming the device.

System and method for dynamic modification of integrated circuit functionality

Routing density estimates within a given integrated circuit are calculated from a proposed floor plan and block interconnect data. The chip is first divided into a number of grid areas, then the routing density is estimated for each grid area. This estimate is calculated by estimating grid areas that signals most likely will cross and summing probabilities. Both horizontal and vertical routing densities are estimated. The estimates for each grid area may then be saved in computer memory, printed, input to a spreadsheet, displayed on the screen, or returned in any other desired format.

Method for estimating and displaying wiring congestion

A high gain, low input capacitance clock buffer includes a plurality of transistors configured to supply an inverted representation of an input reference signal by alternatively switching to provide the output. While either of the transistors is operating to switch the input clock signal, the other transistor is in a stable state. Furthermore, by using n-type FET's, significant power reduction and space savings may be achieved.

Circuit and method for a high gain, low input capacitance clock buffer

A method for increasing the layer density uniformity across a conductive layer, which comprises a plurality of functional blocks, of an integrated circuit is presented. Increased uniformity is achieved by tiling a plurality of capacitors in between the functional blocks. The configuration of the capacitor array and number of the capacitor cells in the array is arranged so as to provide approximate uniformity in the conductor-to-non-conductor density across the entire conductive layer. The capacitor array may be used to reduce power supply switching noise by coupling one or more of the capacitor cells making up the capacitor array between a high power rail and a low power rail.

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Ft. Collins, CO, United States of America

Paul Douglas Nuber