Nxp B.v.

Koninklijke Philips Corporation N.V.

Signify Holding B.v.

Lumileds LLC

Philips Lighting Holding B.v.

Paul Dijkstra

Roelf Anco Jacob Groenhuis

Boudewijn Ruben De Jong

Peter Wilhelmus Maria Van De Water

Cornelis Gerardus Schriks

Johannus Wilhelmus Weekamp

Marcus Franciscus Donker

Lu Fei Zhang

Aernout Reints Bok

Pascal Johannes Theodorus Lambertus Oberndorff

Johannes Wilhelmus Weekamp

Marc Andre De Samber

Hendrik Jan Eggink

Jianghong Yu

Klaas Heres

Daiyu Hayashi

Hans Van Rijckevorsel

Roelf Groenhuis

Michiel Van Der Meer

Geert Steenbruggen

Jan Kloosterman

Arie Jan Hovestad

Maarten Nollen

Methods and apparatus are provided for ultraviolet (UV) water purification, comprising UV-C LED modules having improved light extraction efficiency. UV-C LED dies () are solidly coupled to associated translucent output windows (), such that light is transmitted directly from light-emitting surface(s) of the dies () to output window(s) () of the LED package&#x2014;without propagation across interstitial air gaps. Gas-to-solid (and solid-to-gas) light transition boundaries are thus eliminated, significantly reducing the amount of light lost through inter-medium boundary reflection, and thereby increasing efficiency of light extraction.

UV-C water purification device

A packaged light emitting device dieincludes a package body having a profiled leadframeembedded in a bodyof reflecting material. The leadframeis exposed on mounting surfaceonly on at least one solder bonding area. Solderis present only on the at least one solder bonding areaand not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe. Moreover, the reflecting material can function as a solder resist to self-align the solderto the at least one solder bonding area

Light emitting device package

A light source assembly, a method for producing a light source assembly, and a lamp are provided. In one example, the light source assembly comprises a substrate comprising first and second substrate portions being arranged at a tilt angle (&#x3b1;) to each other forming a V-shaped structure, wherein, at the tip of the V-shaped structure, the first portion comprises a first electrical terminal and the second portion comprises a second electrical terminal. The light source assembly further comprises a light source arranged to bridge a terminal gap between the first and second electrical terminals such that the light source is in electrical connection with the first and second electrical terminals.

Light source assembly and method for producing the same

A packaged light emitting device die includes a package body having a profiled leadframe embedded in a body of reflecting material. The leadframe is exposed on mounting surface only on at least one solder bonding area. Solder is present only on the at least one solder bonding area and not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe. Moreover, the reflecting material can function as a solder resist to self-align the solder to the at least one solder bonding area.

A method of packaging a semiconductor die. The method comprises mounting a semiconductor die to a die attach pad on a carrier and electrically coupling an electrode of the semiconductor die and a contact pad on the carrier with a clip carried by a sacrificial substrate. The method further comprises removing the sacrificial substrate to release the clip. The method may be extended to accommodate a carrier having multiple device regions each with a die attach pad and a contact pad for mounting multiple semiconductor die.

Methods of packaging a semiconductor die and package formed by the methods

An inorganic solder mask () for use as a surface treatment in masking a connection conductor () of a semiconductor chip package () against solder wetting when mounting the chip package () to a printed wiring board () or other substrate. The connection conductor () is partially covered by a metallization contact () formed from a distinct metal. The inorganic solder mask () is applied to an exposed portion () of the connection conductor () not covered by the metallization contact (). The metallization contact () is not coated by the inorganic solder mask (). The presence of the inorganic solder mask () significantly reduces or prevents wetting of the exposed portion () when molten solder is present on the connection conductor () without affecting the solidified solder layer () formed on the metallization contact (). As a result, an extraneous mass of solder does not solidify on the exposed portion () of the connection conductor ().

Surface treatments for contact pads used in semiconductor chip packagages and methods of providing such surface treatments

According to an example embodiment, there is method () for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings on the top-side surface. A laminate material is applied () to the top-side surface of the lead frame. In the laminate material, an air-cavity region and contact regions are defined (). The contact regions provide electrical connections to the predetermined pad landings on the lead frame. With the active circuit surface in an orientation toward the laminate material, the device die is mounted (). The bond pads of the active surface circuit are connected with ball bonds to the predetermined pad landings on the lead frame. An air-cavity is formed between the active surface of the device die and the top-side surface of the lead frame.

Air cavity package for flip-chip

An improved method of etching a structure and a structure etched by the method is disclosed. The bottom side of a leadframe of an IC-package is an example of a structure, which advantageously may be etched with the disclosed method. The method includes the steps of providing an etch mask to the substrate to be etched. The etch mask comprising at least two sub-mask: a first sub-mask covering the area which substantially should remain after the etching process, and a second sub-mask covering an area to be removed in the etching process. The second sub-mask is a sacrificial mask in the form of a grid. The presence of the second sub-mask increases the etching speed in the area covered by it.

Etch method

A carrier () for bonding a semiconductor chip () onto is provided, wherein the carrier () comprises a die pad () and a plurality of contact pads (), wherein each of the plurality of contact pads () comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (), a first buffer layer, and a first conductive layer (). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer () into the first conductive layer (), and at least two of the contact pads () has an ultrafine pitch relative to each other.

Carrier for bonding a semiconductor chip onto and a method of contracting a semiconductor chip to a carrier

A die package () for a semiconductor die (). A plurality of the die packages () are formed on a single carrier () by applying a body () of molding compound across a carrier () with an air cavity () defined in the molding compound about each of a plurality of device regions () of the carrier (). After a semiconductor die () is attached inside the air cavity () of each device region () and electrically connected with at least one contact pad (), a cover () is applied to close all of the air cavities (). Following singulation, each semiconductor die () is located inside the sealed air cavity () of one die package (). The molding compound of each die package () may be locked against movement relative to the device region () of the carrier () by locking features (). The locking features () may constitute portions of contact pads () used to establish electrical communication paths from the semiconductor die () to the environment outside of the package ().

Air cavity package for a semiconductor die and methods of forming the air cavity package

The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Electronic device and method of manufacturing thereof

The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. The element is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

The carrier () comprises a first etch mask (), a first metal layer (), an intermediate layer (), a second metal layer () and a second etch mask (). Both the first and the second etch mask () can be provided in one step by means of electrochemical plating. After the first metal layer () and the intermediate layer () have been patterned through the first etch mask (), an electric element () can be suitably attached to the carrier () using conductive means. In this patterning operation, the intermediate layer () is etched further so as to create underetching below the first metal layer (). After the provision of an encapsulation (), the second metal layer () is patterned through the second etch mask (). In this manner, a solderable device () is obtained without a photolithographic step during the assembly process.

Growing community of inventors

Eindhoven, Netherlands

Paul Dijkstra