Rca Inc.

Thomson Licensing

Thomson Consumer Electronics Inc.

Rca Licensing Corporation

Thomson Licensing S.a.

Paul Dean Filliman

Leopold A Harwood

David J Duffield

Michael Dwayne Knox

Ronald T Keen

Robert Preston Parker

Mark Francis Rumreich

Aaron Hal Dinwiddie

Thomas Edward Horlander

Timothy W Saeger

Karl Francis Horlander

Nathaniel H Ersoz

David Leon Simpson

An apparatus for synchronizing chroma and luma data includes a first handshake block for luma data, a second handshake block for chroma data, and a means for providing a handshake signal to the first block and to the second block based at least in part on a determination that they are both ready to transfer data, and further for inhibiting provision of the handshake signal based at least in part on a determination that at least one of the first block and the second block is not ready to transfer data.

Synchronization of chroma and luma using handshaking

A method for dynamic contrast improvement of video data includes the steps of analyzing a portion of a video frame, and forcing a start of DCI transfer function computations in response to an end of the analysis of the portion of the video frame.

Method for dynamic contrast improvement

An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory ('RAM') and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.

Digital line delay using a single port memory

A source ( ) provides an input signal (S ) to be phase shifted and a combining circuit ( ) concurrently combines first (A), second (B) and third (C) intermediate signals derived from the input signal (S ), and having differing phase shifts (0, &minus;45, &plus;135 deg), to form a phase shifted output signal (S ). A first amplitude controller ( ), responsive to a phase control signal (S ) supplied thereto, varies the amplitudes of the second (B) and third (C) intermediate signals in opposite directions ( ) for controlling the phase of the phase shifted output signal. Additionally, a further amplitude controller ( ) is provided for reducing a tendency for variations in the phase shift control signal (S ) to alter the amplitude of alternating current (FIG. ) and direct current (FIG. ) components of the phase shifted output signal (S ).

Phase shift apparatus

In order to increase the speed of the transfer of control data to an OSD circuit, and to eliminate 'holes' in memory caused by the use of memory mapped registers, dual use is made of the serial data port of the OSD circuit to accomplish two distinct tasks, serial transfer of graphics data and serial transfer of the control data. The on-screen display apparatus includes an OSD circuit for generating an graphics signal for display on a display screen, a controller coupled to the OSD circuit, for controlling the OSD circuit, and a VRAM including a first area for storing graphics data and a second area for storing control data for the OSD circuit. The VRAM has a parallel input/output port coupled to the controller and a serial output port coupled to the OSD circuit, the serial output port conveys the graphics data from the first area of the VRAM to the OSD circuit for processing and display. The controller writes the control data to the second area of the VRAM via the input/output port and the OSD circuit reads the control data from the VRAM via the serial output port during each vertical sync interval.

Bit-mapped on-screen-display device for a television receiver

Automatic letterbox detection

Read column conductors and write column conductors of a memory array are addressed by respective triggerable sequential pulse generators which, upon receiving respective trigger pulses, provide respective read and write address pulses to respective column conductors of the array. Data to be stored is written in parallel to cells of the memory a column at a time at a rate determined by the write sequential pulse generator and is recovered a column at a time at a rate determined by the read sequential pulse generator. Advantageously, (1) the ratio of the read and write rates may be selected to provide time compression, time expansion or constant delay of video data; (2) additionally data may be written and read concurrently without bus contention and (3) addressing is simplified by a timed application of trigger pulses to the pulse generators whereby there is no need for application to the memory of binary addressing data.

Dual port video memory system having pulse triggered dual column

A charge pump arrangement receives a digital error word representing an error signal and charges or discharges a capacitor in accordance with the sign of the error word by an amount that is proportional to the absolute value of the error word. The voltage produced in the capacitor is coupled to a frequency control terminal of a voltage controlled crystal oscillator that is used in, for example, a stereo decoder.

Oscillator frequency control arrangement for a stereo decoder

A controlled crystal oscillator of a stereo decoder of a television receiver using CMOS technology includes first, second and third differential emplifiers that produce corresponding first, second and third pairs of anti-phase output signals. The first and second differential amplifiers have variable gains that vary in opposing manners in accordance with a frequency control signal. The oscillatory signal of a crystal is coupled to corresponding input terminals of the three differential amplifiers such that the phase of the signal that is developed at the input terminal of the third differential amplifier is phase-shifted by approximately 90.degree. relative to those developed at the input terminals of the other two amplifiers. The three pairs of output signals are combined to form a single-ended oscillatory signal that is coupled back to the crystal to complete a regulative feedback path. The frequency of oscillation is determined in accordance with the frequency control signal.

Controlled oscillator

A MOSFET analog signal squaring circuit is disclosed. A first MOSFET has a source electrode coupled to a bias voltage source, a gate electrode coupled to an input terminal, and a drain electrode coupled to an output terminal. A signal inverter is also coupled to the input terminal. A second MOSFET has a source electrode coupled to the bias voltage source, gate electrode coupled to the signal inverter, and a drain electrode coupled to the output terminal. A load impedance is coupled between the output terminal and a supply voltage source.

MOSFET analog signal squaring circuit

A regulating power supply for a video display apparatus includes a switching transistor that periodically energizes a transformer winding. Input switching pulses for the transistor are varied in width and frequency to optimize power transfer via the transformer. The charge and discharge rates of a capacitor determine the pulse width and frequency. The capacitor charging current is selectively switched to be connected to the capacitor while the capacitor discharge current is controlled in response to a feedback signal derived from the regulated voltage level.

Regulating power supply for video display apparatus

A television receiver is arranged to selectively display either information from a broadcast television signal, or information from an auxiliary video signal. The black image reference level associated with the broadcast signal information is sampled and used to automatically establish the black image reference level of the auxiliary video signal.

Television receiver responsive to plural video signals

A television receiver is arranged to selectively display either information from a broadcast television signal or information from an auxiliary video signal, in accordance with the position of a switching network to which the signals are capacitively coupled via respective capacitors. Similar black reference levels are established for the television and auxiliary signals by means of respective clamping circuits, including the coupling capacitors, which operate at different times but with respect to the same clamping reference voltage.

Television receiver with selectable video input signals

In a tuning system for tuning a receiver to various channels, skip channel information is stored in a shift register memory. A channel number counter counts clock pulses which also successively advance data through the shift register. A tuning control signal to tune the receiver to the channel corresponding to the count is generated when the data shifted to the output of the shift register does not define the channel as a channel to be skipped.

Tuning system with provisions for skipping nonpreferred tuning positions

A teletext decoder extracts digital information from a video signal for displaying graphics and textual information embedded in the video signal. The decoder includes a prefix processor responding to user supplied commands for selecting and storing the pertinent embedded information into a memory. The microcomputer reads the data provided by the prefix processor, converts it to pixel words representing picture elements and restores the converted data into the memory. The decoder includes a display processor which reads more than one pixel word at a time when accessing the memory, and translates each pixel word to 3 groups of color codes and to a one-bit transparency code.

Growing community of inventors

Indianapolis, IN, United States of America

Paul Dean Filliman