International Business Machines Corporation

Globalfoundries Inc.

Paul David Muench

Michael Sperling

George E Smith, Iii

James Patrick Eckhardt

Timothy Gerard McNamara

Donald W Plass

Scot H Rider

Shiu Chung Ho

Patrick James Meaney

Michael Stephen Floyd

Jente Benedict Kuang

John Francis Bulzacchelli

Fadi Hikmat Gebara

Wiren Dale Becker

Fariborz Assaderaghi

Seongwon Kim

Joachim Gerhard Clabes

Pawel Owczarczyk

Mangal Prasad

Charlie Chornglii Hwang

Lawrence Joseph Powell, Jr

Lawrence F Wagner, Jr

Kennedy K Cheruiyot

Timothy L Walters

Hector Saenz

Zeynep Toprak-Deniz

Glenn E Holmes

Miguel E Perez

Giacomo Vincent Ingenio

Seth A Erlebacher

Gary Steinbrueck

Michael R Whalen

Alamgir A Tamboli

Anthony E Ciesla

Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.

Charge pump for distributed voltage passgate with high voltage protection

An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.

Distributed environment analog multiplexor with high-voltage protection

According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.

Programable immediate frequency change for digital phase locked loop

A method for operating a charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Charge pump generator with direct voltage sensor

Embodiments relate to a direct voltage sensor and a charge pump system for a computer system. A charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.

Fractional-N spread spectrum state machine

A voltage regulator includes a regulator input connected to a reference voltage; a regulator output that outputs a regulated voltage to an electrical load; a first loop, the first loop configured to receive the reference voltage, the first loop outputting a bias voltage; a second loop, the second loop configured to receive the bias voltage as an input; and a bias voltage capacitor connected to a node between the first loop and the second loop.

Dual loop voltage regulator with bias voltage capacitor

Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider.

Multi-output PLL output shift

A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.

System to improve a multistage charge pump and associated methods

A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Phase locked loop with startup oscillator and primary oscillator

A method and apparatus for generating a voltage that is proportional to an absolute temperature (PTAT voltage). A current generator for generating a current that is proportional to absolute temperature (PTAT current) has an internal resistance and two diodes. The PTAT current is proportional to the resistance, and the temperature coefficient of the PTAT current is defined by the ratio of diode current densities. A feedback circuit has a source follower that is connected to the current generator for driving the output node with a regulated PTAT current wherein the PTAT current is mirrored accurately, providing a constant Vref.

Power supply insensitive PTAT voltage generator

A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.

System to evaluate a voltage in a charge pump and associated methods

A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal. An analysis logic circuit is provided having a plurality of n inputs connected to the outputs of the latches. The analysis logic circuit analyzes the values on the latches to give a measure of jitter.

Phase lock loop jitter measurement

An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

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Poughkeepsie, NY, United States of America

Paul David Muench