Lucent Technologies Inc.

International Business Machines Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Paul David Hendricks

Lane Allen Smith

Donald Raymond Laturell

Steven Brooke Witmer

Jack A Dorler

Dennis C Banker

Frank M Masci

Jonathan Herman Fischer

Ronald Lamar Freyman

Richard Muscavage

Walter S Klara

James R Struk

James M Little

Stephen J Tytran

Tore A Carlson

DC transients are removed from a digital filter such as a sigma delta filter (in particular from a sigma delta high pass filter) from the outset by presetting an input summing node to a sigma delta modulator. While the input summing node may be preset using any appropriate input, in a disclosed embodiment, a sigma delta high pass filter is preset by switching a partial feedback term between an input containing the non-zero preset value and the normal input comprising the output from the input summing node. The preset value is chosen based on the value of the zero of the transfer function of the sigma delta high pass filter, e.g., with the complement of the gain factor.

Reduced DC transients in a sigma delta filter

The present invention provides a digital pre-distortion filter in arrangement with a data access arrangement (DAA) on the component side (e.g., in a modem chipset). This arrangement of the pre-distortion filter outside of the DAA allows digital processes such as digital emulation of the central office impedance to remain unaffected by the pre-distortion in the transmitted signal, allowing the dynamic range of the transmitted signal to be flattened to minimize return loss without complicating the transfer function of the digital emulation of the central office complex load. In the case of a digital emulation filter, placement of a digital pre-distortion filter outside of an analog-to-digital (A/D) digital-to-analog (D/A) loop also minimizes the noise otherwise associated with the use of a pre-distortion filter. Thus, benefits of a pre-distortion filter can be gained without interfering with emulation of impedance, and without causing a significant amount of noise in the transmitted signal.

Placement of a transmit predistortion filter with respect to a data access arrangement

An AC impedance matching architecture which provides programmable AC impedance matching in a given range using a digital filter to filter a signal fed back from the impedance matched line to generate an AC impedance emulation control signal. The AC impedance emulation control signal is combined with a transmit signal (if desired) and drives a voltage controlled current source, which is in parallel with a reference impedance. A voltage is developed across the reference impedance to drive, e.g., the telephone line. The reference impedance is chosen based on a desired maximum AC impedance. The gain of the digital filter, a first order sigma delta filter in the disclosed embodiment, is chosen based on the desired value of the AC impedance. The transfer function of the digital filter is derived based on a desired AC impedance.

Impedance matching with sigma delta filter

A digital system for filtering a single bit input signal according to the transfer function H(z), wherein H(z) has a gain G, a pole at location b , and a zero at location a . The digital system filters the single bit input signal without using computationally expensive multibit multiplication. The digital system achieves these advantages with a digital circuit having a first gain stage generating a gain corrected signal, a delay element generating a delayed gain corrected signal, a feed-forward stage generating a feed-forward signal, and a summer for generating an output signal based upon the sum of the gain corrected signal, the delayed gain corrected signal and the feed-forward signal.

Single bit Sigma Delta filter with input gain

A 2,order digital filter requiring only one sigma delta modulator is created by implementing (1) a 2,order feedforward term created by the cascade of two 1,order elements; (2) a 2,order feedback term created by the cascade of two 1,order elements; and (3) another 2,order feedback term created by the cascade of two more 1,order elements to eliminate the need for another sigma delta modulator to provide a 2,order filter. Thus, for the mere 'cost' of additional feedback loops, which are small in comparison with the size and complexity of another sigma delta modulator, a second sigma delta modulator is not necessary to implement a 2,order digital filter in accordance with the principles with the present invention.

Second order digital filter requiring only one sigma delta modulator

An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2,order biquadratic equations in an overall average of as few as four clock cycles per 2,order biquad. A RAM is used to store the state variables for the 2,order biquadratic equations. The state variable RAM is reset by controlling the clear input of latches at an input and/or the output of the state variable RAM, and the state variable RAM is addressed by a delta counter which is independent of the particular number of filter channels or filter orders implemented. Test patterns may be inserted between functional blocks of an integrated circuit such as the disclosed audio codec by appropriate control of the preset and clear inputs to output latches of the functional blocks.

Distributed gain for audio codec

A scalable overflow clamp for controlling the level of allowable digital signal overflow in a gain scaler/summer having an initial full-scale range and a feedback path for establishing a feedback gain. The clamp includes a range scaler for determining the feedback gain and generating a modified full-scale range relative to the feedback gain. The modified full-scale range defines a substantially constant overflow capability relative to the feedback gain. An overflow detector senses the overflow conditions and a selector responsive to the overflow detector utilizes the modified full-scale range when overflow conditions are sensed.

Scalable overflow clamp and method for a digital gain scaler/summer

A method of breaking up idle tones in a converter is used for gain scaling and summing of digital input signals. The invention achieves this object by introducing dither. Further, the invention optimizes the dither introduced by adapting the magnitude of the dither based on the value of the feedback gain factor of the converter. By adapting the dither in this way, the output idle channel noise can be essentially constant and independent of the scaling factor of the converter.

Dithered digital gain scalar/summer

There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The first switching circuit exhibits a characteristic upon being switched from one of the first or second states to the other, such as from the first state to the second state, that impacts turn-on time of one of the first and second output transistors. The second switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The second switching circuit also exhibits a characteristic that upon being switched from one of the first and second states impacts turn-on time of the other of the first and second output transistors.

Controlled transition time driver circuit

Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The 'inverse' mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode. Transistors embodying the invention may be used to provide relatively constant current sources to numerous utilization means, such as logic or analog circuits. Due to the low VCEi of the 'inverse' mode transistor, the resultant circuits can be operated at a lower operating voltage than prior art circuits. This results in a decrease of power dissipation.

Integrated circuit employing inverse transistors

NOR logic performed by a half current switch emitter follower ('HCSEF') circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ('CSEF') circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.

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Coopersburg, PA, United States of America

Paul David Hendricks