Arm Limited

Paul Darren Hoxey

David Anthony New

Yew Keong Chong

David Michael Bull

Shidhartha Das

Rajiv Kumar Sisodia

Vikash

Sanjay Mangal

Kumaraswamy Ramanathan

Renu Rawat

Gus Wai-Yan Yeung

Paul Stanley Hughes

Andrew John Sowden

Gary Robert Waggoner

Plamen Asenov Asenov

Simon Christopher Reynolds

A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

Memory with a controllable I/O functional unit

The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.

Memory device and method of performing a write operation in a memory device

A latch circuit for retaining and transmitting an input data value is disclosed, along with a memory, and a method for retaining and transmitting data. The latch circuit includes a primary input for receiving a data value, an output for outputting the data value, a data transmission path including a transmitting device for transmitting the data value from the primary input to the output, a feedback loop for retaining the data value, the feedback loop including the transmitting device and a further device. The further device is configured to turn on in response to assertion of an activating signal and to turn off in response to no assertion of the activating signal. The feedback loop not retaining data when the further device is turned off, and the feedback loop further including a multiplexer, and the multiplexer is configured to connect either the data transmitting device to the further device and form the feedback loop or to connect a secondary input to the further device and form a secondary data transmission path from the secondary input through the further device and the transmitting device to the output.

Providing additional inputs to a latch circuit

A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronized with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch.

Supporting scan functions within memories

A data processing system comprising a memory array having a plurality of memory cells and read circuitry for reading a logic value stored in one of the plurality of memory cells. The read circuitry is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.

Apparatus and method for adjusting a supply voltage based on a read result

A memory circuit includes a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit includes a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is configured to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.

Data processing memory circuit having pull-down circuit with on/off configuration

An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.

Power saving in memory arrays

A memory circuit includes a plurality of memory cells which are subject to memory access operations. These memory access operations serve to selectively discharge one or more of the bit lines A, Abar, B, Bbar associated with the memory cells . During a subsequent precharge operation serving to restore the precharged voltage levels of the bit lines A, Abar, B Bbar charge sharing is performed between non-accessed bit lines and those which have been accessed and accordingly at least partially discharged. Also the precharging circuits associated with the non-accessed bit lines contribute towards the precharging operation.

Growing community of inventors

Cambridge, United Kingdom

Paul Darren Hoxey