Globalfoundries Inc.

Paul D Mesa

Qi Xiang

Mahbub Rashed

Lei Yuan

Navneet Jain

Hidekazu Yoshida

Qinglei Wang

Evaluation of electrical accessibility within a layer of a circuit to pin geometries residing within a cell boundary of the circuit is provided. The evaluating includes, for instance, checking along substantially parallel pin geometry access paths of the layer to determine possible points at which a respective pin geometry of the pin geometries within the cell boundary may be accessed. The evaluating also includes identifying which points of the possible points are accessible access points by any route of the possible routes for electrically connecting to a respective pin geometry of the pin geometries from a first side or a second side of the cell boundary, wherein at least one point of the possible points is identified as not being an accessible access point based on the at least one point being inaccessible by the possible routes.

Evaluation of pin geometry accessibility in a layer of circuit

A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Parameterized cell for planar and finFET technology design

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Sunnyvale, CA, United States of America

Paul D Mesa