Intel Corporation

Other

Paul D Madland

Glenn J Hinton

Andrew F Glew

Haitham H Akkary

Kris G Konigsfeld

Jeffrey M Abramson

David B Papworth

Jeffery M Abramson

Mandar S Joshi

Brent E Lince

Michael A Fetterman

Nasser A Kurd

Edward Allyn Burton

Thomas D Fletcher

Robert W Martell

Javed Sabir Barkatullah

Giao N Pham

Gary Leonard Woods

Samie B Samaan

Robert J Murray

Mark A Timko

Douglas A Guddat

Joel C Huang

Monte F Mar

Rob Murray

Atig A Bajwa

Prem Pahlajrai

An apparatus includes a substrate, a target timing circuit, a leakage timing circuit, and a control unit. The target timing circuit and the leakage timing circuits are formed on the substrate. The target timing circuit has a target timing circuit frequency related to a target frequency. The leakage timing circuit has a leakage timing circuit frequency related to a leakage current. The control unit maintains a substantially constant ratio between the target timing circuit frequency and the leakage timing circuit frequency. A method includes generating a first signal related to a target circuit frequency, generating a second signal related to a leakage current, and adjusting a control signal applied to a substrate to maintain a substantially constant frequency ratio between a first signal and the second signal.

Apparatus and method to control self-timed and synchronous systems

A clock generating apparatus is provided that includes a first phase lock loop device powered by an analog (or fixed) power supply voltage and a second phase lock loop device powered by the analog power supply voltage and a digital power supply voltage. The second phase lock loop device to output a clock signal having an adaptive frequency based on the digital power supply voltage.

Adaptive frequency clock generation system

A device and method for probing high-speed local supply voltage fluctuations in VLSI circuits. The device includes a voltage probe coupled to a source of the local supply voltage, the voltage probe detectably emitting infrared radiation having an intensity that is related to a magnitude of the local supply voltage. The method includes emitting infrared radiation having an intensity that is related to the magnitude of the local supply voltage, taking initial measurements of the emitted radiation intensity for a range of supply voltages while digital activity is suspended in a vicinity of the local voltage probe, and compiling a calibration table matching measured intensity values with a magnitude of the supply voltage. Thereafter, digital activity is initiated by running a repetitive pattern through circuitry in the vicinity of the local voltage probe, where the repetitive pattern stimulates local supply voltage fluctuation events. Samples of emitted radiation intensity are taken using a time correlated photon counting or equivalent time sampling process and local supply voltage fluctuations are determined from the detected radiation.

Device and method for probing instantaneous high-speed local supply voltage fluctuation in VLSI integrated circuits using IR emissions

A symmetric differential domino AND gate. In a further embodiment, the symmetric differential domino AND gate has a first evaluation block of transistors and a second evaluation block of transistors, and the first evaluation block and second evaluation block have the same number of transistors and the same size transistors.

Symmetric differential domino &ldquo;AND gate&rdquo;

A circuit includes at least one input, an evaluate pulsed clock, and an output. In one embodiment, the circuit precharges an intermediate node in the circuit in response to a precharge pulsed clock and the evaluate pulsed clock.

Circuit to reduce charge sharing for domino circuits with pulsed clocks

The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.

Method and apparatus for performing a store operation

A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.

Method and apparatus for blocking execution of and storing load

A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

Method and apparatus for calculating effective memory addresses

The precharged bit lines of a memory array are provided with corresponding pass gate devices and a common complementary regulation and control circuitry to keep the precharged bit lines at a voltage below a first voltage and to counter-act any leakage to Vcc through a small current drain to a reference voltage. As a result, the voltage on the precharged bit lines are prevented from moving closer to Vcc, even during a prolonged idle period, and failure will not occur, when the memory cells are accessed again after the prolonged idle period.

Memory arrays with integrated bit line voltage stabilization circuitry

The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.

Method and apparatus for performing multiple load operations to the same

A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.

Out-of-order processor with a memory subsystem which handles

A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.

Computer system that maintains processor ordering consistency by

A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

Method and apparatus for dispatching and executing a load operation to

A method and apparatus for dispatching load operations in a computer system. The present invention includes a method and apparatus for determining when the load operation is ready for dispatched to memory. The load operation is then scheduled to dispatch from memory and then dispatched to memory. In the present invention, a load is determined ready when it is no longer blocked, such that there is no condition which produces a resource or address dependency causing the load to be blocked.

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Beaverton, OR, United States of America

Paul D Madland