Xilinx, Inc.

Imec

Fujitsu Corporation

Interuniversitair Microelektronica Centrum (imec)

Paul Coene

Serge Vernalde

Diederik Verkest

Vincent Nollet

Jean-Yves Mignolet

Theodore Marescaux

Geert Vanmeerbeeck

Hisanori Fujisawa

Bert Geelen

Eddy De Greef

Johan De Geyter

Bart Masschelein

Andrei Bartic

Wilfried Verachtert

Prabhat Avasare

A virtual camera system comprises a plurality of physical cameras and a hardware setup miming software to create virtual viewpoints for the virtual camera system. The position of the physical cameras is constrained, where the main constraint is the overlap between the physical cameras. The present invention provides a method for creating a virtual viewpoint of a plurality of images captured by the plurality of cameras, the images comprising current frames and previous frames. The method comprises creating background frames by combining a set of previous frames; creating a plurality of foreground masks by performing segmentation on the plurality of current frames, the segmentation comprising separating foreground objects from background objects using the created background frames; extracting the foreground objects by AND-ing the plurality of current frames with the created plurality of foreground masks; rendering the foreground objects by using a three dimensional depth-box constrained viewpoint interpolation algorithm on the plurality of current frames, the three dimensional depth box being constructed for each foreground object by exploiting information from the created foreground masks and positioning information of the foreground objects; rendering a view-dependent background image by performing homographic transformations on the created background frames; and creating the virtual viewpoint by superimposing the rendered foreground objects on the rendered background frame.

Virtual camera system

A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.

System and method for hardware-software multitasking on a reconfigurable computing platform

Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).

Heterogeneous multiprocessor network on chip devices, methods and operating systems for control thereof

A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processing units disposed on a layer permitting interconnection between connection nodes; and a mapping unit adapted to substantially simultaneously optimize placement of the tasks on the plurality of programmable processing units and routing of interconnections between the plurality of processing units, the mapping unit adapted to select one placement algorithm among a plurality of predetermined placement algorithms and to select one routing algorithm from a plurality of predetermined placement algorithms, the selection configured to prefer use of non-random algorithms.

System and method for runtime placement and routing of a processing array

Growing community of inventors

Grobbendonk, Belgium

Paul Coene