Juniper Networks, Inc.

Paul Coelho

Jean-Marc Frailong

Jeffrey Glenn Libby

Anurag P Gupta

Sharada Yeluri

Jianhui Huang

A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

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San Jose, CA, United States of America

Paul Coelho