Arm Limited

Prolific, Inc.

Paul Christopher De Dood

Daniel J Albers

Brian Craig Lee

Yew Keong Chong

Andy Wangkun Chen

Gus Wai-Yan Yeung

Marlin Wayne Frederick, Jr

Sriram Thyagarajan

Brian Tracy Cline

Xiaoqing Xu

Tom Shore

Jerry Chaoyuan Wang

David William Granda

James Dennis Dodrill

Thanusree Achuthan

Yanbin Jiang

Sylvia Xiuhui Li

Brian Douglas Ngai Lee

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology. For selected grid locations within the grid array, a lookup operation is performed in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location. The layout of the cell is then generated by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry. This provides an automated mechanism for generating cells whose layouts conform to a target process technology.

Computer implemented system and method for generating a layout of a cell defining a circuit component

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.

Apparatus and method for reduced latency signal synchronization

The present invention comprises a method of optimizing a circuit design having a plurality of library cells. In one embodiment, the method includes the steps of providing a plurality of logically equivalent cells that vary in at least one design parameter, the plurality of logically equivalent cells having a relatively continuous spectrum of values of one of the design parameters, evaluating a selected characteristic of the circuit design; and replacing a cell in the circuit design with a cell an equivalent cell.

Optimization of circuit designs using a continuous spectrum of library cells

The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are in the same fan-in and fan-out cones. This property allows full timing analysis to be performed on a design such that multiple alternatives are explored in parallel and accurate results are obtained. By ordering the choice of cell instances to change and by ordering the alternatives to try, a greater degree of optimization is found earlier in the process.

Parallel optimization using independent cell instances

A method and apparatus for optimizing a circuit design using a library of cells in which a continuous spectrum of cells are provided. A library containing real and virtual cells is used so that cells can be selected across a wide spectrum of a design parameter, such as drive strength. The cells are provided in discrete steps small enough that the effect of having a continuous spectrum of cells is achieved. After optimization, only the cells finally selected need be actually synthesized, and when these constitute a small percentage of the total number of cells, the impact to library size and final placement and routing is minimized. Thus the ability to optimize across a continuous spectrum is achieved while preserving a cell library based design flow.

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Pleasanton, CA, United States of America

Paul Christopher De Dood