3Com Corporation

Paul Chieffo

John J Platko

Michael K Brown

A data transfer technique employs direct memory access (DMA) logic to transfer data to a memory and simultaneously store the data into a buffer that is closely coupled to a processor, enabling the processor to access the data quicker than if accesses to the memory were required. The simultaneous transfer is selectively enabled and disabled by the processor, so that only those portions of the data that are actually needed by the processor are stored into the buffer. The technique is used on a network interface card (NIC), in conjunction with host memory interface logic that transfers packets and packet descriptors from host memory to memory on the NIC. The DMA logic is controlled through the use of DMA descriptors residing on ring data structures in the NIC memory. The processor sets the value of a flag in a descriptor to indicate whether the data involved in a DMA transfer is to be written to the buffer.

Multicast direct memory access storing selected ones of data segments into a first-in-first-out buffer and a memory simultaneously when enabled by a processor

The memory space accessible by a processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal accesses, and are satisfied from the memory or a read buffer. If memory access is required, the processor is stalled until the desired data is returned from the memory. Processor accesses to the other region are regarded as requests to prefetch the data from the memory and place it into a read buffer without stalling the processor. The processor continues program execution while the data is being prefetched. At a later point in program execution, the processor requests the data via the first region. The data likely resides in the read buffer, and can therefore be provided to the processor quickly, resulting in improved performance.

No stall read access-method for hiding latency in processor memory accesses

A method and apparatus for rapidly detecting the source of an interrupt. A multi-bit interrupt state register is provided which registers the occurrence of an interrupt in response to an interrupt event. The outputs of the interrupt state register are coupled to an interrupt vector register which is memory mapped and directly accessible to a processor via load and store instructions. The interrupt vector register is continuously updated to reflect the current state of the interrupt state register. The processor may read the interrupt vector register with low latency, store the contents of the interrupt vector register in a general purpose register within the processor, and determine the source of interrupts via bit test instructions performed on the general purpose register. The bits interrupt state register may be cleared by the processor by upon the issuance of a memory mapped write command to a clear register. Writing to the clear register generates clear pulses for selected bits that result in the clearing of the respective bits of the interrupt state register. Additionally, an interrupt status register is provided which the processor can read over a bus. The interrupt status register contains interrupt events which are accessible by the processor with a greater read access latency than the interrupt state register.

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Bolton, MA, United States of America

Paul Chieffo