Texas Instruments Corporation

Paul C Yu

Ranjit Gharpurey

Shereef Shehata

A method for use in a system including an analog-to-digital converter subsystem (ADC) and a digital-to-analog converter subsystem (DAC), wherein the ADC samples an input signal at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input signal. The method is applicable to such systems in which the DAC includes a plurality of elements, such as capacitors or current sources, each connectable in a plurality of different ways in accordance with the digital outputs so as to contribute a portion of an analog output signal corresponding to the digital output, the magnitude of the portion being determined by a way the element is connected. The method is one for shuffling the elements, and includes the following steps. A plurality of coded analog signals are generated based on the input voltage, each such coded analog signal being above or below a predetermined threshold so as to correspond to a way one of the elements is connected. A predetermined sequence of control codes is provided. The coded analog signals are shuffled in accordance with the sequence of control codes. The shuffled coded analog signals are latched as digital values, and the plurality of elements are connected in ways determined in accordance with the shuffled codes.

High speed analog-domain shuffler for analog to digital converter

A method for shuffling capacitors, for application in a stage of a pipelined analog-to-digital converter that samples an input voltage at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input voltage. The stage includes an amplifier and a plurality of capacitors which may be connected between the input voltage and an AC ground at a first time and which may be connected between the output of the amplifier and an input of the amplifier, or which may be connected between the input of the amplifier and one of a plurality of reference voltage sources at a second time. The method includes the following steps. A plurality of coded input values are provided, each such coded value corresponding to the connection of one of the capacitors between the input of the amplifier and either the at least one voltage sources or the output of the amplifier. A predetermined sequence of control codes is provided. The coded input values are shuffled in accordance with the sequence of control codes. At the second time the plurality of capacitors are connected between the input of the amplifier and the at least one of the reference voltage sources or the output of the amplifier, in accordance with the shuffled coded input values.

Highspeed, high spurious-free dynamic range pipelined analog to digital converter

In a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model. Finally, the cancellation factor is subtracted from an ADC output to substantially reduce and/or effectively cancel the mismatch noise.

Pipelined analog to digital converter using digital mismatch noise cancellation

A method for practice in a pipelined analog to digital converter. The method converts an analog signal to a sequence of digital words, while converting capacitor mismatch in the stages of the ADC into white noise. In the method, for each of one or more of the pipelined stages, first, the plurality of capacitors therein is coupled at a sample time between the stage input port and ground. Second, during an amplifying period following the sample time, one or more of the plurality of capacitors are coupled between a reference voltage and the input port of the amplifier, while the remainder of the plurality of capacitors are coupled between the input port of the amplifier and the output port of the amplifier, such that different ones of the plurality of capacitors are selected, according to a predetermined procedure uncorrelated with the analog signal, for coupling between the stage input port and ground.

Dynamic element matching for converting element mismatch into white noise for a pipelined analog to digital converter

A pipelined analog to digital converter for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a time in a succession of times. The converter includes a sequence of analog to digital converter stages, each such stage generating at least one bit for each such word. A first such stage in the sequence receives the analog signal, and each such stage subsequent to the first stage receives a residue signal from a previous stage in the sequence. Each such stage includes an analog to digital unit that senses a sample of the analog signal and provides one or more bits representing a value of the sample. In at least one of the stages the analog to digital unit comprises a &Sgr;-&Dgr; converter.

Pipelined ADC with noise-shaped interstage gain error

A multi-stage analog-to-digital converter (&ldquo;ADC&rdquo;) for converting an analog input signal to a series of digital values, each having a first plurality of bits, representing the voltage levels of the analog input signal at a corresponding series of sample times. The ADC includes a plurality of analog-to-digital converter stages connected serially in pipeline configuration. One or more of such stages includes an analog-to-digital subconverter, providing a second plurality of bits of the digital value, where the second plurality is smaller than the first plurality, the analog-to-digital subconverter including a plurality of analog-to-digital subconverter substages connected serially in pipeline configuration. Each such subconverter substages provides one or more bits of the second plurality of bits. The nested approach of this invention allows an increased resolution in the first stage of the pipeline which has the benefit of avoidance of capacitor trimming, a more efficient use of the comparators and other circuit components, a relaxation in the comparator offset requirements, and satisfy kT/C noise requirements more easily in submicron low-voltage ADC's.

Nested pipelined analog-to-digital converter

A method for shuffling capacitors from period to sample period in a stage of a multi-stage analog to digital converter (&ldquo;ADC&rdquo;). The ADC stage includes a plurality of capacitors usable for storage of charge during a sample phase and for providing during an amplification phase, in conjunction with an amplifier, an output signal having a voltage representing the difference between the digital output voltage level for the stage and the analog input voltage level for the stage. The method includes the following steps. First, the input is provided to the plurality of capacitors during the sample phase to capture and hold the first analog voltage level at a first time in the sample phase. Then, a selected sub-group of the plurality of capacitors is used as feedback capacitors, while a remaining sub-group of the plurality of capacitors is used as digital to analog subconverter (&ldquo;DASC&rdquo;) capacitors, in conjunction with the amplifier, the selected sub-group and the remaining sub-group being different sets in adjacent sample periods. The selection of capacitors is performed in accordance with a predetermined capacitor shuffling procedure adapted to convert resulting harmonic distortion associated with capacitor mismatch into noise having a spectral amplitude peak placed outside of a predetermined spectral band.

Noise shaping dynamic element mismatch in analog to digital converters

An analog-to-digital converter system,is provided that comprises an analog-to-digital converter pipeline,coupled to a memory system,and a calibration system,. An arithmetic logic unit,receives a raw output from the analog-to-digital converter system,and calibration quantities from the calibration system,to generate a calibrated output. The calibration system,is able to iteratively generate multiple order calibration values that can be used to eliminate capacitor mismatch errors. The techniques described are equally applicable to analog-to-digital converter architectures which resolve multiple bits per stage of the analog-to-digital converter system.

Analog-to-digital converter system having enhanced digital self-calibration

A user transparent self-calibration technique for an analog to digital converter is described. The technique can correct for capacitor mismatch error with minimal additional power consumption. This is done by generating a calibration signal, one for each capacitor whose calibration is desired. The signal is interleaved with the input signal, and digitized by alternating with the input signal digitization using capacitor arrays.

User transparent self-calibration technique for pipelined ADC architecture

An analog-to-digital converter system 10 is provided that comprises two separate banks of capacitors that are configured with a single operational amplifier 30 for each stage 29 within the system 10. The banks of capacitors are used in an interleaved fashion to simultaneously digitize analog input voltages and sample a reference voltage V.sub.REF to enable the digitization of a gain error associated with the operation of amplifier 30. This gain error can be combined with the raw digital output of the converter using an arithmetic logic unit 18 to result in a calibrated output for the system 10.

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Coppell, TX, United States of America

Paul C Yu