Leland Stanford Junior University

Texas Instruments Corporation

Tokyo Electron Limited

Paul C McIntyre

Scott Robert Summerfelt

Luigi Colombo

Mark R Visokay

Takuya Sugawara

Rene Meyer

Wilman Tsai

Wei-Yung Hsu

Robert M Wallace

Glen D Wilk

Krishna Chandra Saraswat

Chi On Chui

John Mark Anthony

Toru Ito

Shu Hu

Christopher E D Chidsey

Baylor B Triplett

Balreen Saini

John D Baniecki

Zhouchangwan Yu

Ferroelectric materials and more particularly cerium-doped ferroelectric materials and related devices and methods are disclosed. Aspects of the present disclosure relate to ferroelectric layers of hafnium-zirconium-oxide (HZO) doped with cerium that enable reliable ferroelectric fabrication processes and related structures with significantly improved cycling endurance performance. Such doping in ferroelectric layers also provides the capability to modulate polarization to achieve a desired operation voltage range. Doping concentrations of cerium in HZO films are disclosed with ranges that provide a stabilized polar orthorhombic phase in resulting films, thereby promoting ferroelectric capabilities. Exemplary fabrication techniques for doping cerium in HZO films as well as exemplary device structures including metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) structures are also disclosed.

Cerium-doped ferroelectric materials and related devices and methods

Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.

Method for forming an interfacial layer on a semiconductor using hydrogen plasma

A device and a method of forming a continuous polycrystalline Ge film having crystalline Ge islands is provided that includes depositing an amorphous Ge (a-Ge) layer on a substrate, oxidizing the top surface of the a-Ge layer to form a GeOlayer, depositing a seed layer of Al on the GeOlayer and catalyzing the Al seed layer, where Ge mass transport is generated from the underlying a-Ge layer to the Al seed layer through the GeOlayer by thermal annealing, where a continuous polycrystalline Ge film having crystalline Ge islands is formed on the Al seed layer.

Metal-induced crystallization of continuous semiconductor thin films controlled by a diffusion barrier

Embodiments of the present disclosure include an anode, devices and systems including the anode (e.g., electrochemical devices and photo-electrochemical devices), methods of using the anode, methods of producing Hand Ofrom HO, Cl, oxidixed organic feedstocks, oxidation for the detection and quantification of chemical species, and the like.

Corrosion-resistant anodes, devices including the anodes, and methods of using the anodes

Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, a memory cell having two sections with outwardly-facing portions, the outwardly-facing portions electrically coupled to electrodes is implemented. The memory cell has an ionic barrier between the two sections. The two sections and the ionic barrier facilitate movement of ions from one of the two sections to the other of the two sections in response to a first voltage differential across the outwardly-facing portions. The two sections and the ionic barrier diminish movement of ions from the one of the two sections to the other of the two sections in response to another voltage differential across the outwardly-facing portions.

Electrochemical memory with internal boundary

Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, resistance-change memory devices are implemented having a pair of electrodes and an intervening electrochemical material. A heating element facilitates changes in resistance of the electrochemical material-region due to changes in ion distribution. The method is implemented without a process for forming a filament-like region in the electrochemical material.

Electrochemical memory with heater

A method and system for forming a nitrided germanium-containing layer by plasma processing. The method includes providing a germanium-containing substrate in a process chamber, generating a plasma from a process gas containing Nand a noble gas, where the plasma conditions are selected effective to form plasma excited Nspecies while controlling formation of plasma excited N species, and exposing the substrate to the plasma to form a nitrided germanium-containing layer on the substrate. A method is also provided that includes exposing a germanium-containing dielectric layer to liquid or gaseous HO to alter the thickness and chemical composition of the layer.

Method and system for forming a nitrided germanium-containing layer using plasma processing

Method for forming a nitrided germanium-containing layer using plasma processing

Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiOequivalent ('T'). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.

High-k dielectric for thermodynamically-stable substrate-type materials

A versatile system providing Cr-based diffusion barriers and electrode structures utilizing such barriers is disclosed, including a semiconductor substrate (), a dielectric layer () disposed upon the substrate, a Cr-based conductive layer () disposed upon the dielectric layer, and an electrode layer () disposed upon the conductive layer.

Versatile system for chromium based diffusion barriers in electrode structures

An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (stepof FIG.) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (stepof FIG.) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.

Method of forming metal oxide gate structures and capacitor electrodes

An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask,the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride,has been shown to yield significantly enhanced adhesion to platinum,as compared to silicon oxide formed by any method. Since silicon nitride,is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the &gE;256 Mbit generations.

Metal patterning with adhesive hardmask layer

A high-k dielectric capacitor structure and fabrication method that incorporates an adhesion promoting etch stop layer 200 to promote adhesion of the bottom electrode 220 to the interlevel dielectric layer 210 and to provide a well controlled, repeatable and uniform recess prior to the dielectric 230 deposition. By using a sacrificial layer 200, for example silicon nitride (Si3N4), this layer can act as an etch stop during the recess etch to eliminate parasitic capacitance between adjacent capacitor cells A and B and can promote adhesion of the bottom electrode material 220 to the substrate 210.

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Sunnyvale, CA, United States of America

Paul C McIntyre