Apd Semiconductor, Inc.

Other

Advanced Power Devices, Inc.

Diodes Inc.

Paul C Chang

Vladimir Rodov

Geeng-Chuan Chern

Wayne Y W Hsueh

Charles Lin

Gary Michael Hurtz

Ching-Lang Chiang

Jianren Bao

Prognyan Ghosh

Michael Chern

Hidenori Akiyama

Dan Dresskell Day

Arthur Ching-Lang Chiang

Yasuo Ohtsuki

Haru Ohkawa

Geeng-Chuan (aka Michael) Chern

Paul G Kostenick

Kenneth P Zaballos

David P Banks

Kerri L Olson

Darrell Darwin Jones

A fabric for container virtual machines (CM) has cross fabric spine switches coupled to spine switches, each spine switch coupled to has a leaf switches, each leaf switch coupled to servers hosting CVM processes. Each of the leaf switches has an uplink port coupled to a spine switch leaf port configured in a mesh. The spine switches have a plurality of uplink ports for coupling to a plurality of cross fabric spine (CFS) ports into a mesh. The cross fabric spine switches keep a CF-NHCIB table of entries containing capabilities, and also a CF-FIB slice table which maintains entries for assignment of CVMs to new spine switches, such as GTID range, MAC Range, IP range associated with a spine port and spine address (MAC and/or IP) for transferring packets through the fabric.

Switch fabric for a data center network having virtual machines

A switch fabric has a plurality of leaf switches, each leaf switch having a local tenant identifier (LTID) table, a local forwarding information base (LFIB) table, and a forwarding engine coupled to the LTID table and LFIB table. Each leaf switch has downlink ports operative on VLAN packets such as those generated by Container/Virtual machines (CVM), each leaf switch also having a reconfigurable uplink port for transmission and reception of VxLAN packets formed from VLAN packets which have a destination address which is not local to a particular leaf switch. The uplink ports are coupled to the leaf ports of one or more spine switches, each spine switch having a Global Forward Information Base (GFIB) table slice coupled to a VxLAN forwarder which receives VxLAN packets, de-encapsulates them and uses the GFIB table slice to form new VxLAN packets transmitted to a different leaf port.

Switch fabric for networked virtual machines

A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Integrated circuit including power diode

An adjustable pulsating submersible () is taught consisting of, a lower pool sweep body () with a resilient skirt () attached underneath. An integrated valve () is positioned within the lower pool sweep body and is used to accomplish a preliminary pre-selected flow adjustment. An upper pool sweep body () is placed over the integrated valve and is attached to the lower pool sweep body with threads in no more than one quarter turn. A flow adjuster () is slid tightly into upper pool sweep body and includes a number of first flow openings (). A flow gate () is slid onto the flow adjuster and may rotate within limits with the flow adjuster. The flow gate incorporates a number of second flow openings () aligned with the first flow openings, when the flow adjuster is manually rotated the second flow openings misalign with the first flow openings providing precise adjustable flow operation.

Adjustable flow pulsating pool sweep

A power device having vertical current flow through a semiconductor body of one conductivity type from a top electrode to a bottom electrode includes at least one gate electrode overlying a gate insulator on a first surface of the body, a channel region of second conductivity type in the surface of the body underlying all of the gate electrode, a first doped region of the second conductivity type contiguous with the channel region and positioned deeper in the body than the channel region and under a peripheral region of the gate electrode, and a second doped source/drain region in the surface of the body abutting the channel region and adjacent to the gate electrode. When the gate is forward biased, an inversion region extends through the channel region and electrically connects the first electrode and the second electrode with a small Vnear to the area between adjacent P bodies being flooded with electrons and denuded of holes. Therefore, at any forward bias this area conducts as an N-type region. When the gate electrode is reverse biased, the long channel region underlying the full length of the gate electrode reduces reverse leakage current.

Power device having reduced reverse bias leakage current

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Method of fabricating power rectifier device to vary operating parameters and resulting device

A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Power diode having improved on resistance and breakdown voltage

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region

A pool cleaner reed valve for a pulsating submersible swimming pool cleaner which has a valve body ( ) configured to fit into a pulsating valve enclosure. The body includes a rectangular inlet end ( ) and an round outlet end ( ) with a pair of fulcrum points ( ) and restricting boundaries ( ) for retaining and confining valve movements. A pair of opposed rigid valve plates ( ) are angularly juxtaposed within the valve inlet end contiguously engaging the fulcrum points and respective restricting boundaries such that each opposed blade rotates inwardly on the fulcrum point until the distal ends intimately engage as influenced by negative fluid pressure applied by a pool pump. A pair of torsion springs ( ) surround each restricting boundary and interface with each valve plate returning them to a parallel position when fluid pressure is terminated. A resilient sleeve ( ) is positioned on each spring for eliminating a metal to metal contact with the spring to the valve plate.

Torsion spring pool cleaner reed valve

A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.

Method of fabricating power VLSI diode devices

A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.

Power device having vertical current path with enhanced pinch-off for current limiting

A power rectifier having low on resistance, fast recovery time and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common conductive layer. This provides a low V path through the channel regions of the MOSFET cells to the contact metallization on the other side of the integrated circuit. A thin gate structure is formed annularly around pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and V .

Discrete integrated circuit rectifier device

A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor. The channel regions are defined by using the photoresist mask for the gate oxide with the photoresist mask isotropically etched to expose a peripheral portion of the gate oxide (and gate electrode) with ions thereafter implanted through the exposed gate for forming the channel region. The source/drain (e.g. source) regions can be formed by ion implantation or by out-diffusion from a doped polysilicon layer.

A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with sidewalls of the grooved surface and ohmic contacts with top portions of the grooved surface. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current. The ohmic contacts of the metal layer increase forward current and reduce forward voltage of the Schottky diode.

Growing community of inventors

Tustin, CA, United States of America

Paul C Chang