International Rectifier Corporation

Infineon Technologies Americas Corp.

Xponent Photonics Inc

Paul Bridger

Robert A Beach

Michael A Briere

Jianjun Cao

Daniel Marvin Kinzer

Oskar Jon Painter

Guido Hunziker

Charles I Grosjean

A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.

Fabrication of semiconductor device using alternating high and low temperature layers

Process for manufacture of super lattice using alternating high and low temperature layers to block parasitic current path

III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.

III-nitride monolithic IC

A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Fabrication of III-nitride semiconductor device and related structures

A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

III-nitride heterojunction device

A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

III-nitride semiconductor device with stepped gate

Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.

Structure and method for III-nitride device isolation

A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

III-nitride semiconductor device with trench structure

Method for fabricating a semiconductor device

Active area shaping for III-nitride devices

III-nitride semiconductor device with stepped gate trench and process for its manufacture

A semiconductor device and a method for manufacturing the device are disclosed in which the semiconductor device includes ohmic contacts on different planes and the method for manufacturing the device includes etching a semiconductor stack of different conductivity semiconductor layers in successive steps to create a first opening of a first width in a first semiconductor layer to expose another semiconductor layer, and then a second opening of a narrower width in the another layer, whereby a portion of the another layer remains exposed for receiving an ohmic contact.

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Altadena, CA, United States of America

Paul Bridger