Data General Corporation

Paul Bowden

John F Pilat

Gary Davidian

Thomas M Jones

David L Houseman

James T Nealon

Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.

Encachement apparatus using two caches each responsive to a key for

Encachement apparatus comprising a plurality of frames which include registers for storing data, one of which frames is selected as a current frame, the encachement apparatus responding to a key for outputting data from the registers in the current frame. The current frame is selected from a succession of frames and during a call operation a new current frame is selected as the frame following the current frame and during a return operation a new current frame is selected as the frame preceding the current frame.

Encachment apparatus using multiple frames and responding to a key to

A content-addressable memory module which performs an associative clear operation in response to a clear signal provided on a clear line. The associative clear operation simultaneously clears all registers in the content-addressable memory module whose contents match bits in a pattern input to the content-addressable memory module. A mask input along with the pattern determines which bits of the pattern are significant for the match. Each register in the content-addressable memory module has a bidirectional match line associated with it. A register's bidirectional match line carries a match signal only if that register contains data matching the pattern bits specified by the mask and the bidirectional match line is receiving a match signal from an external source. Clearing logic associated with each register clears the register when a clear signal appears on the clear line while the register's bidirectional match line is carrying a match signal. In content-addressable memories constructed of such content-addressable memory modules, memory match lines connect match lines associated with a number of registers. The memory match line and all of the match lines connected to it carry match signals only if each of the registers associated with the match lines contains data matching the pattern and mask input to the content-addressable memory module containing the register. The content-addressable memory module further contains logic allowing the use of encoded addresses to address individual registers in the content-addressable memory module.

Content-addressable memory module with associative clear

Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache. The control apparatus responds to the base specifier by causing the first multiplexer to select the displacement value output by the cache and causing the second multiplexer to select one of the values contained in the registers or the value output by the second cache in response to the second displacement. The adder then adds the value selected by the first multiplexer to the value selected by the second multiplexer and outputs the result.

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Raleigh, NC, United States of America

Paul Bowden