Advanced Micro Devices Corporation

Ati Technologies Ulc

Paul Blinzer

Philip Ng

Maggie Chan

Gongxian Jeffrey Cheng

Mark Douglas Hummel

Thomas R Woller

Arshad Rahman

Elene Terry

Ali Ibrahim

Leendert Peter Van Doorn

Vydhyanathan Kalyanasundharam

Alexander J Branover

Maurice B Steinman

Anthony Asaro

Andrew Gregory Kegel

Rex Eldon McCrary

Benjamin T Sander

Philip J Rogers

Anthony T Gutierrez

Jimshed B Mirza

Oleksandr Khodorkovsky

Jeffrey Gongxian Cheng

Michael C Houston

Andrew William Lueck

Walter G Fry

Sonu Arora

Michael L Golden

Francisco Leonel Duran

Ming L So

Nippon Harshadk Raval

Nima Osqueizadeh

Phil Mummah

Magiting M Talisayon

Leendert Van Doorn

Min Zhang

Rex Eldon Mccrary

Krishna Sai Bernucho

Gary H Simpson

Srikanth Masanam

Mom-Eng Ng

Millind Mittal

Nippon HarshadKumar Raval

Korhan Erenben

Leopold Grinberg

Leonard Martin Berk

Upasanah Swaminathan

Samuel Richard Bayliss

David Livingstain Ziman

Ripal Butani

Xiaogang Zheng

Dan P Shimizu

Laura M Smith

Leendert Vandoorn

Methods and apparatuses for transferring data from non-volatile memory to process accelerator memory are disclosed. In one embodiment, a process accelerator issues a transfer request for a resource at a host file system. The process accelerator receives, responsive to the transfer request, data from the host file system, wherein the data corresponds to the resource and the process accelerator receives the data directly from the host file system bypassing staging memory of the host. The process accelerator manipulates the data to obtain the resource. Thus, the process accelerator may obtain the resource directly from the host file system to minimize the number of transfers of the data.

System and method for transferring data from non-volatile memory to a process accelerator

In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

Extended attributes for shared page tables

An apparatus includes a co-processor that provides process operations for a first processor, such as a host processor, that executes one or more applications. The co-processor issues a data load request to a request command queue controlled by a non-volatile memory system, that loads a subset of prestored data from a prestored set of data, such as file data of an application, that is stored in a cache buffer in the non-volatile memory system or system memory, for an operation performed by the co-processor. The co-processor uses the loaded subset of prestored data for the operation. In certain implementations, the co-processor issues the data load request as a direct memory access (DMA) load request for the cache buffer. The prestored set of data includes a prestored set of data from a file storage system. Associated methods are also disclosed.

Apparatus and methods for direct co-processor access to prestored file system data in a non-volatile memory system

An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.

Guest operating system buffer and log accesses by an input-output memory management unit

An electronic device includes a processor that executes one or more guest operating systems and an input-output memory management unit (IOMMU). The IOMMU accesses, for/on behalf of each guest operating system among the one or more guest operating systems, IOMMU memory-mapped input-output (MMIO) registers in a separate copy of a set of IOMMU MMIO registers for that guest operating system.

Providing copies of input-output memory management unit registers to guest operating systems

A technique for accessing accelerated processing device ('APD') memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and accessing memory of the accelerated processing device using the one or both of the first direct mapping unit and the second direct mapping unit.

Techniques for supporting large frame buffer apertures with better system compatibility

Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

Hierarchical asymmetric core attribute detection

An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.

Domain identifier and device identifier translation by an input-output memory management unit

An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

Providing interrupts from an input-output memory management unit to guest operating systems

A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

Networked input/output memory management unit

An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

Method and apparatus for integration of non-volatile memory

A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.

Caching policies for processing units on multiple sockets

A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Method and apparatus for transitioning a system to an active disconnect state

Growing community of inventors

Bellevue, WA, United States of America

Paul Blinzer