Compaq Computer Corporation, Inc.

Paul B Wood

Thomas M Albers

Mark W Welker

John V Eberst

Darwin Fontenot

Richard L Pyra

Jack E Bresenham

Brian F Bounds

Stephen B Preston

A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

Video graphics controller with high speed line draw processor

A graphics device includes first and second endpoint memories where coordinates of a line can be stored. State logic within the graphics device calculates line parameters from the first and second endpoints. The calculated line parameters include a line error term which can be stored in an error term memory. The error term memory is writeable from a source external to the graphics device, such as the CPU of a computer system, so that the external source can modify the contents of the error term register.

Video graphics controller with improved calculation capabilities

A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.

High-speed video display system

Video graphics controller with automatic starting for line draws

Line draw circuitry receives parameters defining first and second endpoints of a line and calculates line parameters based on the first and second endpoints. The line parameters are then stored in a memory. A 'calculate-only' control signals determines whether a line is drawn immediately after calculation (and storing) of the end parameters or whether the line is drawn responsive to a subsequent 'start' signal. If the line is to be drawn responsive to the start signal, the line parameters may be modified prior to drawing the line.

A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. Highlighted pixels in a cursor are displayed by inverting the output of the color palette RAM at cursor locations, for example by way of an exclusive-OR function of the color palette RAM output and a bit corresponding to the comparison of the display location and the desired cursor location. Inversion of the output of the color palette RAM results in higher contrast pixels within the cursor.

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Spring, TX, United States of America

Paul B Wood