Marvell International Limited

Paul B Ricci

Lim Hudiono

Larry L Byers

Gary R Robeck

David M Purdham

Joseba M Desubijana

Michael R Spaur

Yujun Si

Joseph G Kriscunas

Mohammad M Negahban

A disk controller for a hard disk drive includes a disk formatter interfaced via an NRZ bus to a read channel for the disk. The disk formatter includes an LFSR accumulator coupled to the NRZ bus, as well as an LSFR generator that generates synthetic test data for the disk formatter. Under control of a test flag which signifies a test mode, the LSFR generator generates synthetic test data, which is used by the disk formatter to drive the NRZ bus. The LSFR accumulator accumulates data on the NRZ bus, together with data on servo information and sector information. An interface is provided through which the accumulated information is provided to test equipment, for offline analysis of the accumulated information, so as to confirm proper operation of the disk subsystem and/or to detect failures therein.

Method and system for testing a controller of a hard disk drive

Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive

A system includes a receive module, a control module and a read module. The receive module receives a first block that includes first data, a first cyclic redundancy check (CRC) checksum, and a first error-correcting code (ECC) value. The first CRC checksum and the first ECC value include a logical block address (LBA). The control module generates a first derived CRC checksum based on the first data. The first derived CRC checksum does not include the LBA. The read module reads a second block from a parity disk. The second block includes parity data, a second CRC checksum, and a second ECC value. The second CRC checksum and the second ECC value include the LBA.

Method for computing buffer ECC

A cyclic redundancy check (CRC) system for a storage controller comprises a memory that stores first sector data and a corresponding CRC non-zero seed value. A buffer control module includes a CRC module, calculates a CRC value of the first sector data with the CRC module, and combines the CRC value with the CRC non-zero seed value.

System and method for performing parity checks in disk storage systems

A method and system for accumulating CRC value is provided. The system includes a disk controller with a register for staging data segments of variable size, a CRC accumulator for accumulating CRC for data segments of variable size, a feedback multiplier that receives processed upper bits from the CRC accumulator containing previously accumulated CRC and incoming data segments from the register; and bits from the multiplier and the CRC accumulator are added and result from the adding is stored in the CRC accumulator. The method includes processing upper bits from the CRC accumulator containing previously accumulated CRC and incoming data segments, sending the processed results to the multiplier; adding bits from the multiplier and the CRC accumulator, and storing a result from the adding of the bits in the CRC accumulator and the multiplier.

Method and system for performing CRC

A system for maintaining cyclic redundancy check ('CRC') protection of XOR'ed data sectors includes a register that is initialized with a non-zero seed value used for generating sector CRC values. The system includes logic for combining CRC values of at least two sectors and storing a result of the combination modified with a non-zero seeded CRC value.

System and method for performing parity checks in disk storage system

A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

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Coto de Caza, CA, United States of America

Paul B Ricci