Unisys Corporation

Paul B Ricci

Wayne C Datwyler

Theodore C White

Jayesh V Sheth

Dan T Tran

Saul Barajas

David M Kalish

Richard A Cowgill

A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.

Dual bus system with multiple processors having data coherency

A method and implementation is supplied for the synchronous loading and integrity checking of registers located in two different integrated circuit chips. Thus in a computer system having cache memory where the cache memory is sliced into two portions, one of which holds even addresses and the other of which holds odd addresses, there is provided two individual chips each of which has a program word address register which is loaded at the exact same period of time and which is additionally incremented in both cases at the exact same period of time. Further means are provided for checking the integrity of the program word address registers in the first slice and the second slice of the cache in order to insure that they are coherent, or if not coherent, then a disable signal will prevent usage of the address data involved.

Apparatus and method for synchronizing the simultaneous loading of cache

A processor cache memory system utilizes separate cache controllers for independently managing even and odd input address requests with the even and odd address requests being mapped into the respective controllers. Each cache controller includes tag RAM for storing address tags, including a field for storing the least significant address bit, so that the stored tags distinguish between the odd and even addresses. Upon failure of a cache controller, both the even and odd addresses are directed to the operational controller and the stored least significant bit address tag distinguishes between the odd and even input addresses to appropriately generate HIT/MISS signals. The controllers include block address counter logic for generating respective even and odd invalidation addresses for simultaneously performing invalidation cycles thereon when both controllers are operational. When a controller fails, the block address counter logic generates both even and odd block invalidation addresses in the operational controller.

Cache memory system with fault tolerance having concurrently operational

A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

Configurable network using dual system busses with common protocol

A dual bus interface module, providing communication between a processor means and/or translation logic means and a set of dual system busses, provides a programmable transmit logic means which enables bus access for data transfer of commands and message transfer requests to destination modules on said system busses in a manner so as to use any available system bus to complete data transfer requests or to report the status of non-completed requests.

Transmission logic apparatus for dual bus network

A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number 'n' of times, each for a preset predetermined time period of 'p' microseconds.

Programmable timing logic system for dual bus interface

A message transfer system between digital modules where two or more digital modules operate on separate and different message lengths and clock frequencies and where, temporary storage buffer (translator unit) holds messages being transferred between the different digital modules and acts as a speed matching and word length matching buffer unit to permit compatible transfer of message words. Also, the transfer system recognizes when requests are outstanding from both digital modules and can discard a message from a requesting module. Each of the two or more separate digital modules is serviced by dual system busses providing for redundancy of data transfer operations.

Translator system for message transfers between digital units operating

A system for controlling and routing messages and data received from dual system busses, through a bus interface unit, to a protocol translation logic means and to a processor in a central processing module connected onto a dual system bus network. The processor operates at a first clock rate and on a single-word communication protocol while the translation logic means operates at a second rate and multiple-word communication protocol. The processor and translation logic are destination modules which receive the benefit of the receiving control logic system. The receiving control logic system also services external modules on the system bus in order to receive data and control the routing of data to the destination modules. Destination modules which are busy and not ready will cause the system to inform the external transmitting modules that they must retry their transmission. The system also checks the quality of the data on the system busses and informs the processor when errors have been incurred, in addition to informing the originating modules when a transmitted message has been completed.

Receiving control logic system for dual bus network

A bus interface transfer system enables communication to/from dual busses to multiple resource units which include a central processor module and a translation logic unit which permits data transfer between systems having different protocols and different clock rates.

Dual bus interface transfer system for central processing module

A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

Inhibit write apparatus and method for preventing bus lockout

A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

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Laguna Niguel, CA, United States of America

Paul B Ricci