Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

Paul B Rawlins

Phillip M Jones

Robert A Lester

John Edward Larson

David F Heinrich

Patrick Lee Ferguson

Kenneth T Chin

Charles N Shaver

Timothy R Zinsky

Roger A Kaiser, Jr

Charles J Stancil

William J Walker

Hung Q Le

Jens K Ramsey

Robert L Woods

John D Battles

James Andre

Jim Blocker

Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Technique for improving processor performance

Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

Method for improving processor performance

A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.

Next snoop predictor in a host controller

A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.

Coherency control module for maintaining cache coherency in a multi-processor-bus system

A computer system, bus interface unit, and method are provided for securing certain devices connected to an I C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I C bus or addressed device thereon. The unlock signal can be assigned to a particular slot among numerous slots, wherein the slots are arranged in hierarchical order. This allows a system administrator the capability to unlock accesses to protected non-volatile memory, and thereby allowing the system administrator to change passwords within one portion of non-volatile memory, and possibly allowing a lower priority user to access and change a password within another portion of non-volatile memory. The slot which accommodates an unlock signal assigned to the system administrator is altogether separate from a slot assigned to a non-system administrator or user.

Apparatus and method for providing access security to a device coupled upon a two-wire bidirectional bus

A personal computer provides security features enabling control over access to data retained in the computer. The computer is secured by having the system ROM provide a password at power-on to a security device which controls access to the secured features. Once a password has been downloaded to the security device, a Protect Resources command is issued to the security device. To gain access to the secured feature after boot-up, the user provides the correct password to the security device and waits for approval from the security device. Since the security device only verifies the password and does not divulge it, security of the system is enhanced. Once access to protected resources is no longer required, the computer issues another Protect Resources command to the security device to once more lock access to the protected resources.

Security control for personal computer

A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the

System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system

An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.

System and method for serial interrupt scanning

A computer system, bus interface unit and method are provided for securing passwords entered upon a USB input device, such as a USB keyboard. The bus interface unit includes a USB host controller coupled between a USB bus on which the keyboard is configured and another bus on which the system memory is operably connected. The host controller contains registers which keep track of target endpoint addresses of USB devices and, more specifically, address locations (i.e., an input/output address range of to-be-secured data) within those devices. Entry upon a keyboard which falls within the monitored, target endpoint address noted within the host controller will signal the host controller to initiate system management interrupt (SMI), and to execute SMI handler code attributed to SMI. Data from the secured (monitored) target address space is placed within a data buffer of the host controller and eventually to a secured location within system memory.

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Spring, TX, United States of America

Paul B Rawlins