Agere Systems Inc.

Paul B Murphey

Stephen Ward Downey

Edward Belden Harris

Allen Yen

Timothy Scott Campbell

Thomas Michael Wolf

Kelly Hinckley

Paul Edward Wheeler

Daniel M Oman

A process for photoresist layer removal from a semiconductor wafer comprises exposing at relatively high temperature the wafer to an RIE-free microwave-energy-generated plasma of a primary gas mixture, the exposing causing photoresist removal such as by ashing. The method also comprises determining an endpoint to the removal by a determined change in the visible light emanating from a chamber containing the wafer. A multi-step process of the present invention comprises the above method and a preliminary RIE-free microwave-energy-generated plasma that solubilizes polymer on walls of vias of the wafer. This multi-step process also comprises, following the exposing step, a cooling step, a cooling step with a temperature check, and a deglazing step. The deglazing step also uses an RIE-free microwave-energy-generated plasma. Specific gas mixtures for the respective plasmas are exemplified. Other embodiments of methods of the present invention are comprised of less steps, or a consolidation of such steps.

Methods of downstream microwave photoresist removal and via clean, particularly following Stop-On TiN etching

The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.

Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen

A process ( ) for forming a metal interconnect ( ) in a semiconductor device ( ) using a photoresist layer ( ) having a thickness (T) of no more than 0.66 microns without forming a notch in the side ( ) of the interconnect. A reactive ion etching process ( ) used to remove portions of a metal layer ( ) to form the interconnect includes a burst etch step ( ) wherein a first high flow rate ( ) of passivation gas is delivered, followed by a main metal etch step ( ) wherein the flow rate of passivation gas is reduced to a second lower value.

Method for avoiding notching in a semiconductor interconnect during a metal etching step

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Winter Garden, FL, United States of America

Paul B Murphey