Honeywell International Inc.

Honeywell G.m.b.h.

Paul B Gerhart

Dinesh Kumar Kn

Sai Krishnan Jagannathan

Paul Francis McLaughlin

Alexander Chernoguzov

Jethro F Steinman

Michael L Baker

Amol Kinage

W Russell Massey

Angela Lee Lordi

Kamel Zerdoum

Christopher Paul Ladas

Benjamin J Stad

Yasuo Kumeda

A device includes multiple communication interfaces configured to send and receive data over multiple communication paths. The device also includes multiple input/output (I/O) channels configured to communicate with multiple field devices. The device further includes at least one processing device configured to process at least some of the data and control at least one of the field devices based on the processed data. The device may also include an intrinsic safety barrier electrically separating the communication interfaces and the I/O channels. The communication interfaces may include at least one first interface configured to communicate over one or more first communication paths with at least one component of an industrial control system and at least one second interface configured to communicate over one or more second communication paths with at least one other device that is configured to communicate with additional field devices.

Intelligent field input/output (I/O) terminal for industrial control and related system and method

A method includes transmitting a first value to a first slave device via a communication bus, where the first value is within a first range of values associated with the first slave device. The method also includes receiving a second value via the communication bus and detecting a fault when the second value is not within the first range of values associated with the first slave device. Detecting the fault could include detecting a decoder fault when the second value is within a second range of values associated with a second slave device. The method may further include detecting a fault when the second value is within the first range of values associated with the first slave device but does not equal the first value or detecting no fault when the second value equals the first value.

Apparatus and method for fault detection to ensure device independence on a bus

An intrinsic barrier device, method and computer program product for isolating a communication channel of an input/output (IO) module from a field device. The intrinsic barrier device includes a front end having a programming input adapted to receive an analog input (AI), analog output (AO), digital input (DI) or digital output (DO) IO type configuration signal. The intrinsic barrier device also includes a processor to process the IO type configuration signal and an associated memory device storing an intrinsic barrier IO type configuration (IBTC) program. The processor is programmed to implement the IBTC program. The processor, responsive to the IO type configuration signal configures the intrinsic barrier device to operate as the AI, AO, DI or DO for supporting communications through the intrinsic barrier device over the communication channel between the IO module and the field device in the AI, AO, DI or DO.

Intrinsic barrier device with software configurable IO type

An apparatus includes at least one first input/output (I/O) module having multiple first I/O channels. Each first I/O channel is configured to provide a communication path. The apparatus also includes a second I/O module having multiple second I/O channels. Each second I/O channel is configured to provide a redundant communication path for one of the first I/O channels. The apparatus is configured to provide the redundant communication paths for only a subset of the first I/O channels. The first I/O channels may include critical I/O channels and non-critical I/O channels, and the apparatus may be configured to provide the redundant communication paths for only the critical I/O channels. The apparatus can be configured to provide the redundant communication paths for the first I/O channels of a single first I/O module or multiple first I/O modules.

Partial redundancy for I/O modules or channels in distributed control systems

A programmable interface circuit includes channel(s) including a digital logic block having terminals for receiving control signals from a process controller block, for providing logic signals, and terminals for receiving processed signal data. An analog logic block includes a current output digital to analog converter (DAC). An output circuit block includes first and second field terminals (S1,S2) and a sense resistor, wherein current from the DAC is coupled to S1 and the sense resistor is coupled to S2. The analog logic block includes a first and a second multi-channel multiplexer (MUX), an operational amplifier, and an analog to digital converter (ADC). The control signals automatically select from signal modes including an analog output (AO) mode, a digital output (DO) mode, an analog input (AI) mode, a digital input (DI) mode, and at least one additional signal mode provided by adding a sub-mode to the AI mode or DI mode.

Method and apparatus for automatically selecting a plurality of modes for programmable interface circuit by coupling field devices to process controllers

A gateway is used to segment a network, such as a FAULT TOLERANT ETHERNET (FTE) network, into islands. The gateway receives traffic from a first island, forwards part of the traffic to a second island, and blocks another part of the traffic from being forwarded to the second island. The forwarded traffic could include unicast traffic. The blocked traffic could include broadcast or multicast traffic, including diagnostic messages from one or more nodes in the first island.

Apparatus and method for segmenting a communication network

An array of logic gates is configured to implement a predefined strategy for an emergency response system in a hardware-only runtime environment. The array of logic gates receives a plurality of input signals from a set of sensors and actuators located within an industrial processing system. Based upon the received plurality of input signals, the array of logic gates determines an emergency response using the predefined strategy. The array of logic gates implements the emergency response to control the industrial processing system based upon the predefined strategy. The array of logic gates can be reconfigured based upon a change in the predefined strategy.

Safety system based on reconfigurable array of logic gates

A FIFO single port storage device and methods for using the same are disclosed. The FIFO device includes a single port memory for storing data from a host processor. The single port memory is addressed in a sequential and non-random manner, possibly by a monotonically increasing counter. Control circuitry coupled to the counter and the memory allows for the reading/writing of host data from/to the single port memory. Write protect circuitry prevents host writes to the single port memory by entering a write protect state under combinations of the following conditions: (1) the FIFO is full; (2) the FIFO is nearly full, as defined by a host programmable threshold; (3) the host processor commands the FIFO to enter the write protect state; or (4) the host processor acknowledges a FIFO nearly full interrupt. The errant, or stray, write detection circuitry sets a status flag if a write occurs while the FIFO is in the write protect state. The errant write detection circuity detects stray writes to the memory based on the write protect state value and the quantity of data stored in the FIFO, independent of any particular range of memory protected. Information is read from the FIFO by entering the write protect state, determining the quantity of stored FIFO data, reading the data, and resetting the quantity of data to zero. The FIFO device may be implemented using a field programmable gate array, or FPGA.

Single port first-in-first-out (FIFO) device having overwrite protection

A process control system includes a primary processor connected to a primary memory via a bus. The primary processor transfers data to be stored to said primary memory. An apparatus of the present invention connected to the bus, collects predetermined data of the data being transferred simultaneously with the transfer of the data to the primary memory. The predetermined data collected by the apparatus is subsequently transferred to a backup processor controller to update the data base of the backup process controller. The apparatus comprises a storage element which stores the data collected. A logic unit controls the operation of the apparatus including the collection of the predetermined data. A control unit of the apparatus transfers the predetermined data stored in the storage element to the backup process controller.

Apparatus for tracking predetermined data for updating a secondary data

In order to insure the accuracy of information transmitted over a network, the initiation of the message must be unambiguously identified. In the present invention, the intermessage spacing consists of a series of identical logic signals that exceeds a minimum value distinguishing this interval from a message character. The message character has predefined length, with a start bit position logic signal and a stop bit position logic signal bounding the character that has the same number of predetermined logic signals for every message character. The character has at least one additional non-data bit position that has a first logic signal for the initial character of a message and the complementary logic signal for the remaining characters in the message.

Apparatus and method for identification of message initiation in a

In order to prevent `jabber`, the uncontrolled transmission of messages on a communication channel, an antijabber timing unit is frequently used to determine whether a message on the communication channel exceeds the maximum permitted length of time. The present invention provides testing apparatus to determine when the antijabber timing unit is functioning accurately. In addition, protection is provided so that the testing apparatus does not compromise the function of the antijabber timing unit during subsequent message transmission. The antijabber timing unit is also used as part of the enable function for the transmission of messages over a channel to prevent the failure of a single component from resulting in inadvertent transmission of information.

Growing community of inventors

Horsham, PA, United States of America

Paul B Gerhart