Other

O-in Design Automation, Inc.

Sun Microsystems, Inc.

Mentor Graphics Corporation

Paul Andrew Wilcox

Chian-Min Richard Ho

Ping Fai Yeung

Tai An Ly

Kalyana C Mulam

Jing Chyuarn Lin

Lawrence Curtis Widdoes, Jr

Jean-Charles Giomi

David Lansing Dill

Robert Kristianto Mardjuki

Paul Ii Estrada

Thomas P Webber

Paul Estrada, Ii

Paul Il Estrada

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method for automatically searching for functional defects in a description of a circuit

A programmed computer generates descriptions of circuits (called 'checkers') that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of circuit

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

A programmed computer generates descriptions of circuits (called &ldquo;checkers&rdquo;) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of a circuit

A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet. If no older data packet is a member of the same set of which the selected data packet is a member, the selected data packet can be dequeued from the turnstile FIFO without violated the sequential order of data packets of the ordered set to which the data packet belong. Conversely, if an older data packet is of the same ordered set, the selected data packet cannot be dequeued. A turnstile FIFO according to the present invention can be particularly useful in routing traffic within a crossbar between various devices.

Data structure and method for managing multiple ordered sets

A programmed computer generates descriptions of circuits (called &ldquo;checkers&rdquo;) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for managing multiple ordered sets by dequeuing selected data

A portable spot welder includes a hand-held electrode clamp assembly. The hand-held clamp has a fixed electrode and a movable electrode adapted to be moved toward and away from the fixed electrode. A spring loaded toggle is used to pivot the movable electrode to clamp a workpiece between the electrodes to exert a predetermined and repeatable pressure. The invention includes an air cooling system. Air is forced through the electrical cables connecting the hand-held electrode clamp to the welder transformer. At the hand-held clamp, the air escapes to the atmosphere through passageways near the electrodes, thereby enabling heat generated within the cables and at the electrodes to be transferred to the flowing air.

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Palo Alto, CA, United States of America

Paul Andrew Wilcox