Cadence Design Systems, Inc.

Azuro (uk) Limited

Paul Alexander Cunningham

Vivek Chickermane

Steev Wilcox

Krishna Chakravadhanula

Brian Edward Foutz

Stephen Paul Wilcox

Dale Meehl

Louis Christopher Milano

David George Scott

Systems and methods for a sequential decompressor which builds equations predictably provide a first-in, first out ('FIFO') shift register which is fed by a first XOR decompressor and provides outputs to a second XOR decompressor.

Method and system for construction of a highly efficient and predictable sequential test decompression logic

Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator ('PRPG') in the early cycles of an automatic test pattern generation ('ATPG') process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.

Method and system for improving efficiency of sequential test compression using overscan

Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic implemented by a set of XOR gates. The XOR tree compression method may comprise combining signals at each node of the XOR trees according to combination logic implemented by a set of XOR gates.

Method for using XOR trees for physically efficient scan compression and decompression logic

A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Systems and methods for testing integrated circuit designs

Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization

Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.

Method for dividing testable logic into a two-dimensional grid for physically efficient scan

Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Method for using sequential decompression logic for VLSI test in a physically efficient construction

There is disclosed a method, and corresponding apparatus, for determining a clock gating function for a set of clocked state-holding elements, comprising the steps of: for each element, determining the conditions under which the element will hold its current value based only on those inputs which are common to all elements; and combining the conditions to form a gating function.

Generation of clock gating function for synchronous circuit

A method of determining a forced gating function for at least one of a plurality of clocked state-holding elements. The forced gating function compares the input and output of said at least one clocked state-holding element. The method simulates the performance of the element for different implementation conditions; measures the performance of the element for each condition, and determines the implementation of the forced gating function using the measured performances.

Clocked gating based on measured performance

There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

Clock gating for synchronous circuits

A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated circuit design using guard-flops, the method comprising: identifying D-type flip-flops in the first integrated circuit design, and transforming each of the identified D-type flip-flops into a guard-flop comprising a transparent catch latch and a transparent pass latch; generating a catch enable signal for controlling the transparent catch latch from the clock signal and enable signal of the D-type flip-flop in the first integrated circuit design; and generating a pass enable signal for controlling the transparent pass latch based on the catch signals of at least some of the guard-flops that take data from the D-type flip-flop in the first integrated circuit design.

Growing community of inventors

Mountain View, CA, United States of America

Paul Alexander Cunningham