International Business Machines Corporation

Paul Alan Owczarski

Hayden C Cranford, Jr

Martin L Schmatz

Vernon Roberts Norman

Stacy J Garvin

Joseph M Stevens

Joseph Andrew Iadanza

Jonathan H Raymond

Westerfield John Ficken

Eirik Gude

The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

Analog unidirectional serial link architecture

A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.

A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input. The method for operating a serial communications system includes the steps of: (a) providing a plurality of unidirectional serial links, each of the links between a transmitter and a receiver, an output of each transmitter coupled to an input of a corresponding receiver by a medium type with each output having a transmitter terminator and each input having a receiver terminator; (b) terminating variably a selected property of the output of each transmitter to match the medium type coupling the output to the input of the corresponding receiver by use of a transmitter termination configuration signal asserted to the transmitter; and (c) terminating variably a selected property of the input of each receiver to match the medium type coupling the input to the output of the corresponding transmitter by use of a receiver termination configuration signal asserted to the receiver.

Method and system for configuring terminators in a serial communication system

A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

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Raleigh, NC, United States of America

Paul Alan Owczarski