Intel Corporation

Sematech, Inc.

Imec

Cornell University

Katholieke Universiteit Leuven, Ku Leuven R&d

Paul A Zimmerman

Alexander Tregub

Florence Eschbach

Fu-Chang Lo

Chris K Van Peski

Scott Bruce Clendenning

Patricio E Romero

Lars-Ake Ragnarsson

Stefan De Gendt

Ian A Young

Paul B Fischer

Robert L Bristol

Florian Gstrein

Grant M Kloster

James M Blackwell

Wilman Tsai

Christopher Kemper Ober

Wim Deweerd

Emmanuel P Giannelis

Harsono S Simka

David Paul Brunco

Wilfried B Vandervorst

Matty Caymax

Nadine Collaert

Tom Schram

Annelies Delabie

Christof Gabriel Krautschik

Marc Demand

Werner Boullart

Robert Rodriguez

Woo Jin Bae

Robert Edgeworth

Adelina K Shickova

Kazuhiko Yamamoto

Jeffrey Byers

Carita Simons, Legal Representative

Aristeidis Bakandritsos

Michael F Zettel

Markos Trikeriotis

Molecular Graphene (MG) of a physical size and bonding character that render the molecule suitable as a channel material in an electronic device, such as a tunnel field effect transistor (TFET). The molecular graphene may be a large polycyclic aromatic hydrocarbon (PAH) employed as a discrete element, or as a repeat unit, within an active or passive electronic device. In some embodiments, a functionalized PAH is disposed over a substrate surface and extending between a plurality of through-substrate vias. Heterogeneous surfaces on the substrate are employed to direct deposition of the functionalized PAH molecule to surface sites interstitial to the array of vias. Vias may be backfilled with conductive material as self-aligned source/drain contacts. Directed self-assembly techniques may be employed to form local interconnect lines coupled to the conductive via material. In some embodiments, graphene-based interconnects comprising a linear array of PAH molecules are formed over a substrate.

Low-defect graphene-based devices and interconnects

Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD)

Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrWO) or hafnium tungstate (HfWO). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (TSVs)

A method and system for cleaning lithography components including contacting a substrate having residue including organic compounds and graphitic carbon deposited on a surface thereof with hydrogen peroxide vapor. The hydrogen peroxide vapor is irradiated with electromagnetic radiation having a wavelength in the range of 100 nm to 350 nm forming hydroxyl radicals. The hydroxyl radicals react with the residue to remove the residue from the surface of the substrate.

Cleaning organic residues from EUV optics and masks

A pellicle membrane is mounted between an outer frame and an inner frame. At least one of the frames is attached to the reticle without using conventional adhesives. The pellicle and reticle may be used in a lithography system. The pellicle allows radiation to pass through the pellicle to the reticle and may prevent particles from passing through the pellicle.

Mounting a pellicle to a frame

A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SFbased metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vcontrol and increased drive current on MuGFET devices is achieved.

Use of F-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies

One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Method for fabricating a high-K dielectric layer

Method, apparatus, and composition of matter suited for use with, for example, immersion lithography. The composition of matter includes hafnium dioxide nanoparticles having diameters less than or equal to about 15 nanometers. The apparatus includes the composition of matter, a light source, a platform for supporting a work piece, and a lens element. The method includes providing a light source, providing a lens element between the light source and a work piece, providing the composition of matter between the lens element and the work piece, and exposing the work piece to light provided by the light source by passing light from the light source through the lens element and the composition of matter to the work piece.

Immersion lithography using hafnium-based nanoparticles

The present invention relates generally to non-aggregating nanoparticles, including ligand capped metal oxide nanoparticles. Methods for their synthesis and methods for their use, for example, for improved immersion lithography processes, are also disclosed.

Non-aggregating nanoparticles and the use thereof

The present invention relates generally to the fields of semiconductor lithography. More particularly, it concerns methods, compositions, and apparatuses relating to 157 nm and 193 nm soft pellicles and the use of perfluorinated polymers in the creation of pellicles.

Method for making soft pellicles

The present invention relates generally to the fields of semiconductor lithography. More particularly, it concerns methods, compositions, and apparatuses relating to 157 nm, 167 nm, 193 nm, 248 nm, 365 nm, and 436 nm soft pellicles and the use of perfluorinated polymers in the creation of pellicles.

Soft pellicle and method of making same

The invention is related to an ALD method for depositing a layer including the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.

Atomic layer deposition method for depositing a layer

Soft pellicle for 157 and 193 nm and method of making same

Growing community of inventors

Phoenix, AZ, United States of America

Paul A Zimmerman