Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Paul A Santeler

Gary W Thome

Sompong Paul Olarig

Robert A Lester

John Edward Larson

Kenneth A Jansen

John MacLaren

George D Megason

Siamak Tavallaei

Dwight L Barron

Christian H Post

Brett D Roscoe

Jeffery L Galloway

Eric Rose

Tim W Majni

Anisha Anand

Gerald K Kleyn

John A Landry

Gary J Piccirillo

Michael J Collins

Randy M Bonella

Jerome J Johnson

Michael Lawrence Sabotta

David R Wooten

Roger E Tipley

Patrick Lee Ferguson

Lee B Hinkle

Michael G Abernathy

Angie M Fletcher

Roy E Thomas, Iii

Managing multiple cartridges that are electrically coupled together includes obtaining general purpose command instructions from a chassis with a cartridge where the cartridge has a unique application and is connected to the chassis and further operating the unique application based on the general purpose command instructions.

Managing multiple cartridges that are electrically coupled together

A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Main memory controller adapted to correct corrupted data by xoring corrupted data to directly generate correct data

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

Removable memory cartridge system for use with a server or other processor-based device

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate &ldquo;hot-plug&rdquo; capabilities utilizing its removable memory cartridges.

Raid memory

Fault tolerant memory

A computer system includes a memory bus, a connector and a controller. The connector is configured to receive a memory module and prevent removal of the memory module from the connector in a first state. The connector allows removal of the memory module from the connector in a second state. The controller is configured to change a connection status between the connector and the memory bus in response to the connector changing from one of the states to the other state. A central processing unit of the computer system is configured to use the memory bus to store data in the memory module.

Installation and removal of components of a computer

The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors. Formed on the I/O board are (1) a peripheral interconnect bus structure connected to the first sets of connector electrical contacts, (2) an electrical bus structure connected to the second sets of connector electrical contacts and associated cable connectors, and (3) an intercontroller bus structure connected between the second sets of connector electrical contacts and enabling the two array controller cards to communicate with one another independently of the peripheral interconnect bus structure. Electrical cables are interconnected between the electrical bus structure and the back plane circuit boards to couple the array controller cards thereto in a redundant control manner without requiring direct cable connection to either of the array controller cards.

Electronic apparatus having I/O board with cable-free redundant adapter

A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller takes advantage of different speed memory devices by operating each memory device at optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine has completed its function, it notifies a related state machine that it can now proceed and thereafter waits for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory system includes a single chip comprising a plurality of flip-flops which provides all of the address and control signals to a memory device so that a clock cycle can be saved because of reduced skew of the signals. These flip-flops are synchronously clocked by a common clock and provide the final output of the address and control signals for the DRAM devices.

Memory controller having all DRAM address and control singals provided

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Cypress, TX, United States of America

Paul A Santeler