U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Nxp B.v.

Koninklijke Phillips Electronics N.v.

Paul A Moore

Brian John Minnis

Anthony R Cusdin

Michael E Barnard

Alan J Davie

Colin L Perry

Johannes O Voorman

Richard F Mitchell

Philip D White

Adrian W Payne

Anthony Richard Cusdin, Deceased

Astrid Paula Maria Schweer

Christopher S Barnes

Brian J Minnis

A transmitter has a power amplifier () to amplify an input signal having amplitude modulation, a supply voltage controller () to control a supply voltage of the power amplifier () according to the envelope, a sensor (R) for sensing a modulation of a current drawn by the power amplifier (), a delay detector () for detecting a delay of the controlled supply voltage relative to the sensed current, and a delay adjuster () for compensating the relative delay according to the detected delay. By sensing a current drawn, the delay detected can include any delay contributed by the power amplifier () up to that point, and yet avoid the more complex circuitry needed to derive the delay from an output of the power amplifier. Thus the distortion and out of band emissions caused by differential delays can be reduced more effectively.

RF transmitter with compensation of differential path delay

A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator () for deriving a demodulated bit rate signal, means () for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means () for selecting the threshold value for comparison with the current bit signal (S) in response to a sequence of N bits (where N is at least 2) (B, B) received prior to the current bit (B) and means () for using the current bit to update the selected threshold value. Also disclosed is a method of dc offset correction.

Receiver having a variable threshold slicer stage and a method of updating the threshold levels of the slicer stage

A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter () for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter () for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter () is terminated, the other (I) is digitised by a non-complex ADC (), then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter () are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs () is possible, thereby avoiding duplication of circuitry and providing significant power savings.

Radio receiver

A radio receiver configurable to operate in either a low-IF or a zero-IF mode comprises a quadrature down-converter () for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter () for performing image rejection filtering. One of the outputs (Q) of the filter () is terminated, the other (I) is passed to a non-complex ADC (). The output from the ADC is processed digitally then a quadrature signal generator () generates quadrature-related IF signals which are passed to a down-converter () for conversion to baseband signals. By enabling analogue-to-digital conversion and channel filtering to be performed at IF on non-complex signals, significant power savings are possible. Further, the flexibility of the receiver is enhanced, enabling it to operate efficiently in both low-IF and zero-IF modes.

A polyphase receiver comprises an RF front end (to) for receiving a wanted data signal modulated on a carrier signal and for producing quadrature related low IF signals, an image rejection filter formed by a polyphase filter () for filtering the quadrature related low IF signals, soft limiting means () for compressing the dynamic range of the filtered quadrature related IF signals and a signal demodulator () for recovering the data signal. The soft limiting means () has a characteristic which is substantially linear at signal levels 10 dB below a predetermined minimum wanted signal level, moves into compression for higher signal levels and hard limits at substantially 10 dB above the desired receiver sensitivity which avoids degrading the sensitivity of the receiver.

Polyphase receivers

A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter is terminated, the other (I) is digitised by a non-complex ADC then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs is possible, thereby avoiding duplication of circuitry and providing significant power savings.

A low IF receiver suitable for use in cellular and cordless telephones and TV tuners, comprises input signal receiving means( ), quadrature related frequency down conversion means including first and second mixing means( ) having first inputs( ) coupled to the input signal receiving means and a local oscillator means( ) for generating a local oscillator signal having a frequency offset from a nominal centre frequency of the input signal coupled to second inputs( ) of the first and second mixing means, a channel selectivity polyphase filtering means( ) for selecting a wanted channel signal from outputs of the first and second mixing means, means( ) for detecting when the quality of the frequency down converted signal becomes unacceptable due a large adjacent channel interfering component and means responsive to said detection for changing the local oscillator frequency by at least twice the low IF or one channel bandwidth to displace the large interfering component outside the bandwidth of the channel selectivity polyphase filtering means( ) and simultaneously changing the centre frequency of the polyphase filter.

Low IF receiver

A phasing receiver includes a quadrature mixing arrangement for frequency converting an input or high IF information signal to a pair of quadrature related low IF signals. The low IF signals are applied to a polyphase filter which functions as a low pass and adjacent channel rejection filter. One or more elements effecting a fine adjustment of relative phase away from quadrature and/or relative amplitude away from equality of the low IF signals are incorporated in information or oscillator signal paths in or about the mixing arrangement or a superhet stage preceding the quadrature mixing arrangement. These elements effect a predistortion of relative phase and/or relative amplitude of the low IF signals in order to compensate for mismatches in an input stage of the filter, and thereby improve image rejection by the filter.

Phasing receivers

An integrated receiver in which in order to permit ac-coupling between stages and to remove the effects of strong directly detected amplitude modulated interfering signals lying within the input band of the receiver, the input signal is frequency down converted using a local oscillator signal which provides an intermediate frequency (F.sub.if) which lies above the frequency of the directly detected interferer (F.sub.AMP). The outputs from the frequency down converters (14, 16, 18, 20) are ac coupled to filtering means the outputs of which are applied to an equalizer (52). The filtering means may comprise a polyphase filter (50), the frequency response of which is distorted by the ac coupling capacitors (54, 56). By applying the outputs of the filtering means to the equalizer (52) substantially all the distortion introduced by the ac coupling capacitors (54, 56) on the filter response is removed to provide an acceptable signal for detection and recovery of the modulating signal.

Integrated receiver

A communications receiver such as an integrated zero IF receiver comprises an input for receiving an input signal and a zero IF frequency down conversion circuit coupled said input and constructed to provide quadrature related signals (I,Q) at a substantially zero intermediate frequency. In order to balance the signal paths, at least one capacitance in each of the quadrature related zero IF signal paths of the frequency down conversion circuit comprises at least two integrated capacitors connected in anti-parallel. By fabricating the integrated capacitances in this way the symmetry of the circuit is maintained which enhances significantly the second-order inter-modulation performance.

Communications receivers

An automatic gain control strategy for zero IF receivers in which the gain of low pass filters (20,22) is altered whilst keeping their bandwidths substantially constant. The low pass filters (20,22) are implemented as gyrator filters, each of which comprise at least one pair of transconductors, the ratio of the transconductances of which are adjustable in such a manner as to maintain the product of their transconductances constant. An electronic signal for adjusting the ratio of the transconductances is derived from an estimate of the instantaneous signal amplitude of the received signal.

Zero IF receivers

A radio receiver has a frequency down conversion stage including a first passive filter tuned to a lower frequency. An amplifier functioning as a voltage-to-current converter includes a resistor (60) which can be shunted by a second passive filter in response to actuation of symmetrically arranged switching devices. When the second passive filter shunts the resistor, the overall pass band is raised to a higher frequency. Additionally, the amplifier has a lower noise figure when the second passive filter shunts the transconductor.

Receiver having an adjustable bandwidth filter

A cascaded amplifier is comprised of a number of amplifying stages connected in cascade such as the dual emitter-coupled amplifier shown. A first pair of transistors (14,20) provides limiting amplification and a second pair of transistors (16,18) with degeneration (22,24) provide linear amplification. Each pair of transistors is driven by a current source (28,26) which supplies a current (IT, IT2) proportional to absolute temperature (PTAT). The small signal amplification is then substantially independent of temperature and the value of the limited output is proportional to absolute temperature. This latter effect is countered by including a translinear variable current gain amplifier (54,56,58,60) in the last dual-gain stage of the cascaded amplifier to modify the output voltage in a manner inversely proportional to absolute temperature. A transfer function may thus be provided which is substantially independent of temperature.

Cascaded amplifier having temperature compensation

A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The transconductance amplifier circuit (TAC) may be of any suitable type which has its transconductance linearly proportional to its emitter currents. In a refinement of the circuit, the current-to-voltage converter function of the current mirrors is carried out by the second transistors (70,71) and the transistors (82,83) of the current mirror circuits (80,81) are omitted.

Four quadrant multiplier circuit and a receiver including such a circuit

A transconductance amplifier comprises first and second input transistors having base electrodes to which an input voltage (Vi) is applied. A constant current source is connected to the emitters of the input transistors. Outputs are derived from their collector electrodes. A tapped impedance having two or more segments (R0 to RN,RN to R0) is connected between the base electrodes of the input transistors. The base electrodes of a plurality of further transistors are connected to respective taps of the tapped impedance. The emitter areas of these further transistors increase from each end of the tapped impedance towards the center of the tapped impedance. The emitters of the further transistors are connected to the current source and the collectors are connected to a junction which is connected to means for computing the combined base currents of the further transistors from the combined collector currents at said junction. The computed current is supplied by a current mirror circuit to the center of the tapped impedance to pull up the voltage at the center. The tapped impedance can have an increased resistance without unduly loading a preceding stage.

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Seaford, United Kingdom

Paul A Moore