International Business Machines Corporation

Cornell University

Paul A Merolla

Dharmendra S Modha

John Vernon Arthur

Andrew S Cassidy

Rodrigo Alvarez-Icaza Rivera

Jun Sawada

Bryan L Jackson

Pallab Datta

John Edward Barth, Jr

Filipp A Akopyan

Subramanian Srikanteswara Iyer

Steven Kyle Esser

Myron Dale Flickner

Benjamin G Shaw

Arnon Amir

Leland Chang

Daniel Joseph Friedman

Robert K Montoye

Jose A Tierno

Jae-sun Seo

Bernard V Brezzo

Rajit Manohar

Alyosha C Molnar

Rathinakumar Appuswamy

William P Risk, Iii

Rodrigo Alvarez-Icaza

Michael V DeBole

Rodrigo Alvarez Icaza Rivera

Gregory Sean Corrado

Brian Taba

John E Barth

David J Berg

Rodrigo Alcarez-Icaza Rivera

An event-driven neural network including a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array that has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

Neuromorphic event-driven neural computing architecture in a scalable neural network

Embodiments of the invention relate to a neural network system for simulating neurons of a neural model. One embodiment comprises a memory device that maintains neuronal states for multiple neurons, a lookup table that maintains state transition information for multiple neuronal states, and a controller unit that manages the memory device. The controller unit updates a neuronal state for each neuron based on incoming spike events targeting said neuron and state transition information corresponding to said neuronal state.

Hardware architecture for simulating a neural network of neurons

Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.

Scalable neural hardware for the noisy-OR model of Bayesian networks

Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.

Yield tolerance in a neurosynaptic system

Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.

Providing transposable access to a synapse array using a recursive array layout

The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

A multiplexed neural core circuit according to one embodiment comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.

Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency

Embodiments of the invention provide a method for mapping a bipartite graph onto a neuromorphic architecture comprising of a plurality of interconnected neuromorphic core circuits. The graph includes a set of source nodes and a set of target nodes. The method comprises, for each source node, creating a corresponding splitter construct configured to duplicate input. Each splitter construct comprises a first portion of a core circuit. The method further comprises, for each target node, creating a corresponding merger construct configured to combine input. Each merger construct comprises a second portion of a core circuit. Source nodes and target nodes are connected based on a permutation of an interconnect network interconnecting the core circuits.

Mapping graphs onto core-based neuromorphic architectures

Embodiments of the invention provide a system and circuit interconnecting peripheral devices to neurosynaptic core circuits. The neurosynaptic system includes an interconnect that includes different types of communication channels. A device connects to the neurosynaptic system via the interconnect.

Peripheral device interconnections for neurosynaptic systems

One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.

Dual deterministic and stochastic neurosynaptic core circuit

Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.

Globally asynchronous and locally synchronous (GALS) neuromorphic network

Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

Memory-mapped interface to message-passing computing systems

One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a metadata analysis unit for analyzing metadata information associated with one or more portions of an adjacency matrix representation of the neural network, and a mapping unit for mapping the one or more portions of the matrix representation onto the neurosynaptic substrate based on the metadata information.

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.

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Palo Alto, CA, United States of America

Paul A Merolla