Src Computers, Inc.

Paul A Leskar

Jon M Huppenthal

A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors ('MAP') in the memory subsystem. The MAP may comprise one or more field programmable gate arrays ('FPGAs') which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory (&#x201c;ROM&#x201d;) located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access (&#x201c;DMA&#x201d;) modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in the programmable hardware.

Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem

An enhanced memory algorithmic processor (&ldquo;MAP&rdquo;) architecture for multiprocessor computer systems comprises an assembly that may comprise, for example, field programmable gate arrays (&ldquo;FPGAs&rdquo;) functioning as the memory algorithmic processors. The MAP elements may further include an operand storage, intelligent address generation, on board function libraries, result storage and multiple input/output (&ldquo;I/O&rdquo;) ports. The MAP elements are intended to augment, not necessarily replace, the high performance microprocessors in the system and, in a particular embodiment of the present invention, they may be connected through the memory subsystem of the computer system resulting in it being very tightly coupled to the system as well as being globally accessible from any processor in a multiprocessor computer system.

Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer

A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (&ldquo;MAP&rdquo;) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (&ldquo;FPGAs&rdquo;) which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory (&ldquo;ROM&rdquo;) located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access (&ldquo;DMA&rdquo;) modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in the programmable hardware.

A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors ('MAP') in the memory subsystem. The MAP may comprise one or more field programmable gate arrays ('FPGAs') which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory ('ROM') located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access ('DMA') modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in the programmable hardware.

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Colorado Springs, CO, United States of America

Paul A Leskar